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| ||<<BR>> Hwanseok Yeo received B.S. and M.S. degrees in electrical engineering from Sogang University, Seoul, Korea in 2003 and 2005, respectively. Also, he received Ph.D. degree from Seoul National University, Seoul, Korea, in 2017.From 2005 to 2011, he was a engineer with System LSI, Samsung Electronics, Korea, working on PLL, DLL designs for high-speed interfaces, LCD timing controllers and mobile application processors. Since March 2017, he has been a senior research engineer in the same company. His research interests include mixed-signal systems such as PLL, CDR, and ADC and their design methodologies.<<BR>><<BR>>'''Contact Information'''<<BR>>''- Email: hwanseok.yeo@samsung.com''<<BR>>'' || {{attachment:hsyeo.jpg|hsyeo|width="150"}} || | ||<<BR>> Hwanseok Yeo received B.S. and M.S. degrees in electrical engineering from Sogang University, Seoul, Korea in 2003 and 2005, respectively. Also, he received Ph.D. degree from Seoul National University, Seoul, Korea, in 2017. From 2005 to 2011, he was a engineer with System LSI, Samsung Electronics, Korea, working on PLL, DLL designs for high-speed interfaces, LCD timing controllers and mobile application processors. Since March 2017, he has been a senior research engineer in the same company. His research interests include mixed-signal systems such as PLL, CDR, and ADC and their design methodologies.<<BR>><<BR>>'''Contact Information'''<<BR>>''- Email: hwanseok.yeo@samsung.com''<<BR>>'' || {{attachment:hsyeo.jpg|hsyeo|width="150"}} || |
About Hwanseok Yeo
Biography
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Research Interests
- High-Performance Digital PLL and CDR Design
- Cell-Based Design Flow
Publications
- Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," International Solid-State Circuits Conference (ISSCC), 2016.
- J. Kim, H. Yeo, S. Ryu, “Synthesizing Method of Signal Having Variable Frequency and Synthesizer of Signal Having Variable Frequency,” US Patent App. 2014/604533, filed Jan. 2015.
- Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, and Jaeha Kim "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function" IEEE Jounal of Solid-State Circuits (JSSC), Aug. 2014.
- Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," Custom Integrated Circuits Conference (CICC), Sep. 2013.
- Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," Symposium of VLSI Circuits, 2013.
- 여환석, 류시강, 최윤주, 김재하, "PVT-Insensitive, Adaptive-Bandwidth Digital PLL Design with Constant Relative-Gain DCO," 한국전자파학회 하계종합학술대회, 2013년.
My Research Projects
- Fast Chirp Frequency Synthesizer PLL for FMCW Radar
- Multiphase PLL with a hybrid injection-locking
- Wide frequency range PLL with fractional divider
- Adaptive-bandwidth PLL with constant relative gain DCO