Main Research Directions

Gordon Moore, in his seminal article in 1965, made a projection that the number of transistors on a chip will increase exponentially over the years. This projection is now known as Moore’s law. In the very same paper, he also listed anticipated challenges for sustaining such phenomenal growth in the level of integration. Those included excessive power dissipation and unmanageable design complexity/cost. More than 40 years later, Moore’s concerns have come true. Those are the key challenges that IC designers are facing today.

Our overall research objective is to address these challenges with unique mixed-signal system approaches. Our research efforts can be classified into the following three categories:

Continue on the design of energy-efficient, high-performance digital I/O interfaces through mixed-signal architectures combining both strengths of analog and digital.
Pioneer in the area of analog/mixed-signal design and verification methodologies to facilitate efficient design and reuse despite aggressive technology scaling.
Explore new applications where mixed-signal approaches can benefit: for instance, nano/bio/medical sensor interfaces and power electronics.

MICS Research Direction

High-Performance, Low-Power Interconnects

High-speed transceivers and serializer/deserializers
Precise timing generation circuits (PLL/DLLs)
Clock and data recovery loops (CDRs)

Design and Validation Methodologies for Analog and Mixed-Signal Systems

Leveraging linear abstraction to simplify analog verification
Intent-based design methodologies: circuit optimization, modeling, and coverage analysis
Verifying if intent is realized properly: e.g. global convergence analysis
Enabling robust design of mixed-signal "A+D" systems
CircuitBook: a shared repository of analog circuit blocks

Exploring New Areas based on Our Expertise

Systems traditionally designed based on ADC and DSP: sensor interfaces and smart power ICs
Adopt the unique "A+D" systems in high-speed links to achieve high performance and low power
Integrated mixed-domain systems: e.g. bio-sensors, power converters, silicon photonics, etc.

Our Research Collaborators/Sponsors

MICS Research Sponsors

MICS Publications

Journal Publications

Seyoung Kim and Jaeha Kim, "Reachability Analysis for Nonlinear Analog/Mixed-Signal Circuits With Trajectory-Based Reachable Sets," IEEE Access, 2023
Seyoung Kim, Seungho Yang, Hyein Lim, Hyein Lee, Jongwook Jeon, Jung Yun Choi, and Jaeha Kim, "Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits," IEEE Access, 2023
Sigang Ryu, Chan Young Park, Wooryeol Kim, Seuk Son, and Jaeha Kim, "A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC," IEEE Transactions on Circuits and Systems I (TCAS-I), 2021
Seuk Son, Sigang Ryu, Hwanseok Yeo, and Jaeha Kim, "A 2x Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery," IEEE Journal of Solid-State Circuits (JSSC), 2019
Sigang Ryu, Seuk Son, and Jaeha Kim, "An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery," IEEE Transactions on Circuits and Systems I (TCAS-I), 2019
Yunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, and Jaeha Kim, "CHIMERA: A Field-Programmable Mixed-Signal IC with Time-Domain Configurable Analog Blocks," IEEE Journal of Solid-State Circuits (JSSC), 2018
Minbok Lee, Joonseok Yang, Myeong-Jae Park, Sung-Youb Jung and Jaeha Kim, "Design and Analysis of Energy-Efficient Single-Pulse Piezoelectric Energy Harvester and Power Management IC for Battery-Free Wireless Remote Switch Applications," IEEE Transactions on Circuit and Systems I (TCAS-I), 2017
Minbok Lee, Yunju Choi, Jaeha Kim, "A 500-MHz, 0.76-W/mm2 Power Density and 76.2% Power Efficiency, Fully- Integrated Digital Buck Converter in 65nm CMOS", IEEE Trans. Industry Applications, 2016
Minbok Lee and Jaeha Kim, "Design of 93% Energy Efficiency Buck-Type Capacitor Charger IC in 250nm CMOS", IEEE Trans. Industry Applications, 2016
Jieun Jang, Jaeha Kim, "PPV-based Modeling and Event-driven Simulation of Injection-locked Oscillators in System Verilog," IEEE Trans. Circuits and Systems I (TCAS-I), 2015
Yoontaek Lee, Taewook Kang, and Jaeha Kim, "A 9-11 bits Phase-Interpolating Digital Pulse-Width Modulator with 1000X Frequency Range", IEEE Trans. Industry Applications, 2015
Seung-Heon Baek and Jaeha Kim, "Design of Low-Power and Low-Latency 256-Radix Crossbar Switch Using Hyper-X Network Topology," Journal of Semiconductor and Technology Science (JSTS), Feb. 2015
Sung-Joon Lee and Jaeha Kim, "A 256-Radix Crossbar Switch Using Mux-Matrix-Mux Folded-Clos Topology," Journal of Semiconductor and Technology Science (JSTS), Dec. 2014
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, and Jaeha Kim "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function" IEEE Jounal of Solid-State Circuits (JSSC), Aug. 2014.
Byoung-Joo Yoo, Woo-Rham Bae, Jiho Han, Jaeha Kim, and Deog-Kyoon Jeong, "Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit," IEEE Trans. Very Large Scale Integration Systems (TVLSI), 2013
Sangho Youn and Jaeha Kim, "Preventing Global Convergence Failure in Mixed-Signal Systems via Indeterminate State (‘X’) Elimination," IEEE Trans. Circuits and Systems I (TCAS-I), 2013
Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyunghoon Kim, E-Hung Chen, Brian Leibowitz, and Jaeha Kim, "A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizing Receiver Front-End and Its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm," IEEE J. Solid‐State Circuits (JSSC), Nov. 2013.
Myeong-Jae Park and Jaeha Kim, "Pseudo-linear Analysis of Bang-bang Controlled Timing Circuits," IEEE Trans. Circuits and Systems I (TCAS-I), June. 2013.
J. Kim, E.-H. Chen, J. Ren, B. S. Leibowitz, P. Satarzadeh, J. L. Zerbe, C.-K. K. Yang, "Equalizer Design and Performance Trade-offs in ADC-based Serial Links," IEEE Trans. Circuits and Systems I (TCAS-I), Sep. 2011.
J. Kim, K. D. Jones, M. A. Horowitz, “Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch,” IEEE Trans. Circuits and Systems I (TCAS-I), July 2010.
J. Kim, J.‐K. Kim, B.‐J. Lee, D.‐K. Jeong, “Design Optimization of On‐chip Inductive Peaking Structures for 0.13‐um CMOS 40‐Gb/s Transmitter Circuits,” IEEE Trans. Circuits and Systems I (TCAS-I), Dec. 2009.
J. Kim, B. S. Leibowitz, J. Ren, C. J. Madden, “Simulation and Analysis of Random Decision Errors in Clocked Comparators,” IEEE Trans. Circuits and Systems I (TCAS-I), Aug. 2009.
J. Kim, “On‐Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs”, IEEE Trans. Circuits and Systems II (TCAS-II), June 2009.
J.‐K. Kim, J. Kim, G. Kim, D.‐K. Jeong, “A Fully Integrated 0.13‐um CMOS 40‐Gb/s Serial Link Transceiver,” IEEE J. Solid‐State Circuits (JSSC), May 2009.
J. Kim, “Adaptive‐Bandwidth Phase‐Locked Loop with Continuous Background Frequency Calibration”, IEEE Trans. Circuits and Systems II (TCAS-II), Mar. 2009.
M.‐S. Hwang, J. Kim, D.‐K. Jeong, “Reduction of Pump Current Mismatch in Charge‐Pump PLL,” IET Electronics Letters, Jan. 2009.
W.‐J. Choe, B.‐J. Lee, J. Kim, D.‐K. Jeong, G. Kim, ʺA Single‐Pair Serial Link for Mobile Displays for Clock Edge Modulation Scheme,ʺ IEEE J. Solid‐State Circuits (JSSC), Sep. 2007.
J. Kim, J.‐K. Kim, B.‐J. Lee, N. Kim, D.‐K. Jeong, W. Kim, “A 20‐GHz Phase‐Locked Loop for 40Gb/s Serializing Transmitter in 0.13‐um CMOS,” IEEE J. Solid‐State Circuits (JSSC), Apr. 2006.
E. Alon, J. Kim, S. Pamarti, K. Chang, M. Horowitz ʺReplica Compensated Linear Regulators for Supply‐Regulated Phase‐Locked Loops,ʺ IEEE J. Solid‐State Circuits (JSSC), Feb. 2006.
H.‐R. Lee, M.‐S. Hwang, B.‐J. Lee, Y.‐D. Kim, D. Oh, J. Kim, S.‐H. Lee, D.‐K. Jeong, W. Kim, “A 1.2V‐only 900‐mW 10Gb Ethernet Transceiver and XAUI Interface with Robust VCO Tuning Technique,” IEEE J. Solid‐State Circuits (JSSC), Nov. 2005.
J. Kim and D.‐K. Jeong, “Multi‐gigabit‐rate Clock and Data Recovery Based on Blind Oversampling,” IEEE Communication Magazine, Dec. 2003.
J. Kim, M. A. Horowitz, and G.‐Y. Wei, “Design of CMOS Adaptive‐bandwidth PLL/DLLs: A General Approach,” IEEE Trans. Circuits and Systems II (TCAS-II), Nov. 2003.
J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, M. Shankaradas, “Self‐Biased, High‐Bandwidth, Low‐Jitter 1‐to‐4096 Multiplier Clock‐Generator PLL,” IEEE J. Solid‐State Circuits (JSSC), Nov. 2003.
J. Kim and M. A. Horowitz, “Adaptive Supply Serial Links with Sub‐1V Operation and Per-pin Clock Recovery,” IEEE J. Solid‐State Circuits (JSSC), Nov. 2002.
J. Kim and M. A. Horowitz, “An Efficient Digital Sliding Controller for Adaptive Power Supply Regulation,” IEEE J. Solid‐State Circuits (JSSC), May 2002.
G.‐Y. Wei, J. Kim, D. Liu, S. Sidiropoulos, M. Horowitz, “A Variable‐Frequency Parallel I/O Interface with Adaptive Power‐Supply Regulation,” IEEE J. Solid‐State Circuits (JSSC), Nov. 2000.

Conference Publications

International

Jeong Woo Min and Jaeha Kim, "XSNN: a System-Level Simulator for Spiking Neural Network with Neuron Circuits and Synapse Devices," IEEE International SoC Conference (ISOCC), 2022.
Seung-Heon Baek and Jaeha Kim, "A Gradient Descent Calibration Method to Mitigate Process Variations in Analog Synapse Arrays," International Conference on Electronics, Information, and Communication (ICEIC), 2022.
Seyoung Kim and Jaeha Kim, "Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis," IEEE International SoC Conference (ISOCC), 2021.
Chan Young Park and Jaeha Kim, "Event-Driven Modeling and Simulation of 5G NR-Band RF Transceiver in System Verilog," IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2021.
Chan Young Park and Jaeha Kim, "A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise Amplifiers," Design and Verification Conference US (DVCON), 2021.
Seyoung Kim and Jaeha Kim, "An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilog," Design and Verification Conference US (DVCON), 2021.
Nayoung Choi, and Jaeha Kim, "Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations," International Conference on Computer-Aided Design (ICCAD), 2020.
Seuk Son, Hwanseok Yeo, Sigang Ryu, and Jaeha Kim, "A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery," IEEE Asian Solid-State Circuits Conference (ASSCC), 2018.
Yoontaek Lee, Sangwoo Han, and Jaeha Kim, "A 1-MHz Leakage-compensating Bootstrap Driver for Normally-on Depletion-mode GaN FET," Energy Conversion Congress & Expo (ECCE), 2017
Hyunseung Lee, Eunseo Kim, and Jaeha Kim, A 220-V AC, LUT-controlled 6-segmented LED driver with background calibration," Energy Conversion Congress & Expo (ECCE), 2017
Sung-Youb Jung, Minbok Lee, Joonseok Yang and Jaeha Kim, "A 20nW-to-140mW Input Power Range, 94% Peak Efficiency Energy-Harvesting Battery Charger with Frequency-Sweeping Input Voltage Monitor and Optimal On-Time Generator," Symposium on VLSI Circuits (SOVC), 2017
Sung-Youb Jung, Myeongjae Park, Minbok Lee, Joonseok Yang and Jaeha Kim, "Time Slot Optimization Algorithm for Multisource Energy Harvesting Systems," European Solid-State Circuits Conference (ESSCIRC), 2016
Yoontaek Lee, Jeongyeol Kwon, and Jaeha Kim "Power Loss Analysis of Switched-mode Converter Circuits in XMODEL," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2016
Yunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, and Jaeha Kim, "A Field-Programmable Mixed-Signal IC with Time-Domain Configurable Analog Blocks," Symposium on VLSI Circuits (SOVC), 2016
Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," International Solid-State Circuits Conference (ISSCC), 2016
Eunseo Kim and Jaeha Kim, "A Constant Relative-Gain DCO with Pseudo-Exponential DAC and FVC Feedback for a Constant Loop-Bandwidth PLL", International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2015
Minbok Lee and Jaeha Kim, "Design of 93% Energy Efficiency Buck-Type Capacitor Charger IC in 250nm CMOS," ECCE-Asia, 2015
Yoontaek Lee, Juyun Lee, and Jaeha Kim, "GaN FET-based Synchronous Buck Converter with 10-bit 4-MHz Digital Pulse Width Modulator," ECCE-Asia, 2015
Juyun Lee, Jeong Yeol Kwon, and Jaeha Kim, "Modeling and Simulation of Nonlinear Transient Responses of High-Voltage Wordline Generators in NAND Flash Memories," International SoC Design Conference (ISOCC), 2015
Taehoon Jeong and Jaeha Kim, "A 110-V AC, 17.1-W Multi-Segmented LED Driver with 96.2% Power Factor," Applied Power Electronics Conference and Exposition (APEC), 2015
Joonseok Yang, Minbok Lee, Myeong-Jae Park, Sung-Youb Jung and Jaeha Kim, "A 2.5-V, 160-μJ-Output Piezoelectric Energy Harvester and Power Management IC for Batteryless Wireless Switch (BWS) Applications," Symposium of VLSI Circuits (SOVC), 2015
Minbok Lee, Yunju Choi and Jaeha Kim, "A 0.76W/mm2 On-chip Fully-Integrated Buck Converter with Negatively-Coupled, Stacked-LC Filter in 65nm CMOS," Energy Conversion Congress & Expo (ECCE), 2014
Yoontaek Lee, Taewook Kang and Jaeha Kim, "A 9~11-bit Phase-Interpolating Digital Pulse-Width Modulator with 1000:1 Frequency Range," Energy Conversion Congress & Expo (ECCE), 2014
Taewook Kang and Jaeha Kim, "Design and Analysis of 37.5% Energy-Recycling Flyback-Type Class-D Gate Driver IC with 5-to-15V Level-Conversion," Energy Conversion Congress & Expo (ECCE), 2014
Taewook Kang, and Jaeha Kim, "Design and Analysis of a Buck-Type Class-D Gate Driver IC," Applied Power Electronics Conference and Exposition (APEC), 2014
Wootaek Lim, Joonseok Yang, Myeongjae Park, Minho Won, and Jaeha Kim, "A 5V, 33-kHz, 0.7-uW Pulse Generation Circuit for Ultra-Low-Power Boost Charging Energy Harvesters," Asian Solid-State Circuits Conference(A-SSCC), Nov. 2013.
Taewook Kang,Yoontaek Lee, Myeong-Jae Park, and Jaeha Kim, "A 15-V, 40-kHz Class-D Gate Driver IC with 62% Energy Recycling Rate," Asian Solid-State Circuits Conference(A-SSCC), Nov. 2013.
Taehwan Kim, Do-Gyoon Song, Sangho Youn, Jaejin Park, Hojin Park and Jaeha Kim, "Verifying Start-up Failures in Coupled Ring Oscillators in Presence of Variability Using Predictive Global Optimization," International Conference on Computer-Aided Design (ICCAD), Nov. 2013.
Gwangsun Kim, John Kim, Jung Ho Ahn, Jaeha Kim, "Memory-centric System Interconnect Design with Hybrid Memory Cubes," International Conference on Parallel Architectures and Compilation Techniques (PACT), Oct. 2013.
Jaeha Kim, Jiho Lee, Do-Gyoon Song, Taehwan Kim, Kyung-Hoon Kim, Seobin Jung, Sangho Youn, "Discretization and Discrimination Methods for Design, Verification, and Testing of Analog/Mixed-Signal Circuits," Custom Integrated Circuits Conference (CICC), Sep. 2013.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," Custom Integrated Circuits Conference (CICC), Sep. 2013.
Ji-Eun Jang, Si-Jung Yang, Jaeha Kim, "Event-Driven Simulation of Volterra Series Models in SystemVerilog," Custom Integrated Circuits Conference (CICC), Sep. 2013.
Hyun-Chang Kim, Chang Soo Yoon, Deog-Kyoon Jeong, and Jaeha Kim, "A Single-Inductor, Multiple-Channel Current-Balancing LED Driver for Display Backlight Applications," ECCE, Sep. 2013.
Sangho Youn and Jaeha Kim, "Global Convergence Analysis – Detecting and Preventing Startup Failures in Mixed-Signal Systems," SRC TECHCON. Sep. 2013.
Taehwan Kim, Sangho Youn, and Jaeha Kim, "Verifying Start-up Failures in Coupled Ring Oscillators in Presence of Variability Using Predictive Global Optimization," SRC TECHCON, Sep. 2013.
Jihwan Choi and Jaeha Kim, "A Compact Impedance Measurement System for Bio Sensing Applications on Programmable System-on-Chip (PSoC)," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June. 2013.
Si-Jung Yang, Ji-Eun Jang, and Jaeha Kim, "Event-Driven Simulation of Nonlinear Voltage-Controlled Oscillators in SystemVerilog," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June. 2013.
Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," IEEE Symp. on VLSI Circuits (SOVC), June. 2013.
Jieun Jang, Myeong-Jae Park and Jaeha Kim, "An Event-Driven Simulation Methodology for Integrated Switching Power Supplies in SystemVerilog," ACM/IEEE Design Automation Conference (DAC), June. 2013.
Taewook Kang and Jaeha Kim, "Investigations on On-Chip Planar Inductor Design with Post-Processed Magnetic Core for DC-DC Converter Applications", ECCE Asia, June. 2013.
Yunju Choi and Jaeha Kim, "Robust Random Chip ID Generation with Wide-Aperture Clocked Comparators and Maximum Likelihood Detection," IEEE International Symposium on Circuits and Systems (ISCAS), May. 2013.
Dogyoon Song and Jaeha Kim, "A Low-Power High-Radix Switch Fabric Based on Low-Swing Signaling and Partially-Activated Input Lines," International Symposium on VLSI Design, April. 2013.
Sangho Youn and Jaeha Kim, "Markov Network Based Equivalence Checking in Mixed-Signal Systems," Frontiers in Analog CAD (FAC), Feb. 2013.
Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyung Hoon Kim, and Jaeha Kim, "A 2.3-mW, 5-Gb/s Decision-Feedback Equalizing Receiver Front-End with Static-Power-Free Signal Summation and CDR-based Precursor ISI Reduction," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2012.
Kyung Hoon Kim, Jaeha Kim, "Fault Coverage Analysis on Analog/Mixed-Signal Circuits Based on Statistical Dissimilarity," poster session in IEEE Int’ Test Conf., Nov. 2012.
Jihyun Ryoo, Seuk Son, and Jaeha Kim, "A 25–FO4, 81-mW Radix-64 Crossbar Switch with Partially-Activated Input and Output Lines," International SoC Design Conference, 2012.
Ji-Eun Jang, Myeong-Jae Park, Dongyun Lee and Jaeha Kim "True Event-Driven Simulation of Analog/Mixed-Signal Behaviors in System Verilog: A Decision-Feedback Equalizing (DFE) Receiver Example," IEEE Custom Integrated Circuits Conference (CICC), Sep, 2012.
Myeong-Jae Park, Hanseok Kim, Seuk Son and Jaeha Kim "A 5-Gbps 1.7pJ/bit Ditherless CDR with Optimal Phase Interval Detection," IEEE Custom Integrated Circuits Conference (CICC), Sep. 2012.
Seobin Jung, Yunju Choi, Jaeha Kim, "Variability-Aware, Discrete Optimization for Analog Circuits," ACM/IEEE Design Automation Conference (DAC), June 2012.
Jaeha Kim, Sigang Ryu, Byoungjoo Yoo, Hanseok Kim, Yunju Choi, and Deog-Kyoon Jeong, "A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs," IEEE International Symposium on Circuits and Systems (ISCAS), May 2012.
Eunchul Kang and Jaeha Kim, "A Single-Stage Off-line LED Driver IC with Hysteric Power Factor Correction Control," Applied Power Electronics Conference and Exposition (APEC), Feb. 2012.
Myeong-Jae Park, Hanseok Kim, Minbok Lee, Jaeha Kim, "Fast and Accurate Event-Driven Simulation of Mixed-Signal Systems with Data Supplementation," IEEE Custom Integrated Circuits Conference (CICC), Sep. 2011.
Kyunghoon Kim, Jaeha Kim, "Investigations on the Use of Negative-Resistance Terminations for Multi-Drop Bus Channels," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2011.
Seobin Jung, Sangho Youn, Jaeha Kim, "Analysis on Performance Controllability under Process Variability: A Step Towards Grid-Based Analog Circuit Optimizers", Frontiers in Analog Circuit (FAC) Synthesis and Verification, July 2011.
Sangho Youn, Jaeha Kim, Mark Horowitz, "Preventing Global Convergence Failures in Mixed-Signal Systems by Eliminating Indeterminate States", Frontiers in Analog Circuit (FAC) Synthesis and Verification, July 2011.
Eunchul Kang, Jaeha Kim, Dohwan Oh, Dongjin Min, "A 6.8-W Purely-Resistive AC Light-Emitting Diode Driver Circuit with 95% Power Factor", International Conference on Power Electronics, May 2011.
S. Youn, J. Kim, M. A. Horowitz, "Global Convergence Analysis of Mixed-Signal Systems", ACM/IEEE Design Automation Conf. (DAC), June 2011.
J. Kim, J. Ren, B. S. Leibowitz, P. Satarzadeh, A. Abbasfar, J. Zerbe, "Equalizer Design and Performance Trade-offs in ADC-based Serial Links," Custom Integrated Circuits Conference (CICC), Sept. 2010.
B. C. Lim, J. Kim, M. A. Horowitz, "An Efficient Test Vector Generation for Checking Analog/Mixed-Signal Functional Models", ACM/IEEE Design Automation Conf. (DAC), June 2010.
M. Jeeradit, J. Kim, M. Horowitz, "Intent-leveraged Optimization of Analog Circuits via Homotopy," Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2010.
J. Kim, M. Jeeradit, B. Lim, M. A. Horowitz, "Leveraging Designer’s Intent: A Path Toward Simpler Analog CAD Tools", Custom Integrated Circuits Conference (CICC), 2009.
J. Kim, J. Ren, M. A. Horowitz, “Stochastic Steady‐State and AC Analyses of Mixed‐Signal Systems,” ACM/IEEE Design Automation Conf. (DAC), July 2009.
J. Kim, M. Jeeradit, A. Varzaghani, I. Huang, “A Schematic Symbol Library for Collaborative Analog Circuit Development Across Multiple Process Technologies,” ACM/IEEE Design Automation Conf. (DAC), Users Track, July 2009.
J. Kim, B. S. Leibowitz, M. Jeeradit, “Impulse Sensitivity Function Analysis of Periodic Circuits,” ACM/IEEE Int’l Conf. on Computer‐Aided Design (ICCAD), Nov. 2008.
J.‐K. Kim, J. Kim, D.‐K. Jeong, “A 20‐Gb/s Full‐Rate 27‐1 PRBS Generator Integrated with 20‐GHz PLL in 0.13‐m CMOS,” IEEE Asian Solid‐State Circuits Conf. (ASSCC), Nov. 2008.
B. S. Leibowitz, J. Kim, J. Ren, C. Madden, “Characterization of Random Decision Errors in Clocked Comparators,” IEEE Custom Integrated Circuits Conference (CICC), Sep. 2008.
M. Jeeradit, J. Kim, B. S. Leibowitz, P. Nikaeen, V. Wang, B. Garlepp, C. Werner, ʺCharacterizing Sampling Aperture of Clocked Comparators,ʺ IEEE Symp. on VLSI Circuits (SOVC), June 2008.
J.‐K. Kim, J. Kim, G. Kim, D.‐K. Jeong, ʺA 40Gb/s Transceiver in 0.13um CMOS Technology,ʺ IEEE Symp. on VLSI Circuits (SOVC), June 2008.
K. D. Jones, J. Kim, V. Konrad, “Some ‘Real World’ Problems in Analog and Mixed‐Signal Domains,” Designing Correct Circuits, Mar. 2008.
J. Kim, K. D. Jones, M. A. Horowitz, ʺVariable Domain Transformation for Linear PAC Analysis of Mixed‐Signal Systems,ʺ ACM/IEEE Int’l Conf. on Computer‐Aided Design (ICCAD), Nov. 2007.
J.‐K. Kim, J. Kim, S.‐Y. Lee, S. Kim, D.‐K. Jeong, ʺA 26.5‐37.5 GHz Frequency Divider and a 73‐GHz‐BW CML Buffer in 0.l3-um CMOS,ʺ IEEE Asian Solid‐State Circuits Conf., Nov. 2007.
J. Kim, K. D. Jones, M. A. Horowitz, ʺFast, Non‐Monte‐Carlo Estimation of Transient Performance Variation Due to Device Mismatch,ʺ ACM/IEEE Design Automation Conf. (DAC), June 2007.
S.‐Y. Lee, J. Kim, B.‐J. Lee, H.‐C. Kim, H.‐H. Ko, D. Dan Cho, D.‐K. Jeong, ʺA Bandpass Sigma‐Delta Interface IC for Sacrificial Bulk Micromachined Inertial Sensors,ʺ IEEE Asian Solid‐State Circuits Conf. (ASSCC), Nov. 2006.
J. Kim, J.‐K. Kim, B.‐J. Lee, N. Kim, D.‐K. Jeong, and W. Kim, “A 20‐GHz Phase‐Locked Loop for 40Gb/s Serializing Transmitter in 0.13um CMOS,” IEEE Symp. on VLSI Circuits (SOVC), June 2005.
B.‐J. Lee, M.‐S. Hwang, J. Kim, D.‐K. Jeong, and W. Kim, “A Quad 3.125Gbps Transceiver Cell with All‐Digital Data Recovery Circuits,” IEEE Symp. on VLSI Circuits (SOVC), June 2005.
J. Kim, J.‐K. Kim, B.‐J. Lee, M.‐S. Hwang, H.‐R. Lee, S.‐H. Lee, N. Kim, D.‐K. Jeong, and W. Kim, “Circuit Techniques for a 40Gb/s Transmitter in 0.13-um CMOS,” IEEE Int’l Solid‐State Circuits Conf. (ISSCC), Feb. 2005.
H.‐R. Lee, M.‐S. Hwang, B.‐J. Lee, Y.‐D. Kim, D. Oh, J. Kim, S.‐H. Lee, D.‐K. Jeong, W. Kim, “A Fully Integrated 0.13-um CMOS 10Gb Ethernet Transceiver with XAUI Interface,” IEEE Int’l Solid‐State Circuits Conf. (ISSCC), Feb. 2004.
J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, M. Shankaradas, “Self‐Biased, High‐Bandwidth, Low‐Jitter 1‐to‐4096 Multiplier Clock‐Generator PLL,” ACM/IEEE Design Automation Conference (DAC), Jun. 2003.
J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, M. Shankaradas, “Self‐Biased, High‐Bandwidth, Low‐Jitter 1‐to‐4096 Multiplier Clock‐Generator PLL,” IEEE Int’l Solid‐State Circuits Conf. (ISSCC), Feb. 2003.
J. Kim, M. A. Horowitz, “Adaptive Supply Serial Links with Sub‐1V Operation and Per‐pin Clock Recovery,” IEEE Int’l Solid‐State Circuits Conf (ISSCC), Feb. 2002.
J. Kim, M. A. Horowitz, “An Efficient Digital Sliding Controller for Adaptive Power‐Supply Regulation,” IEEE Symp. on VLSI Circuits (SOVC), Jun. 2001.
S. Sidiropoulos, D. Liu, J. Kim, G.‐Y. Wei, M. Horowitz, “Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers,” IEEE Symp. on VLSI Circuits, Jun. 2000.
G.‐Y. Wei, J. Kim, D. Liu, S. Sidiropoulos, M. Horowitz, “A Variable‐Frequency Parallel I/O Interface with Adaptive Power‐Supply Regulation,” IEEE Int’l Solid‐State Circuits Conf. (ISSCC), Feb. 2000.

Domestic

Deokjin Kim, and Jaeha Kim, "Zero-Crossing Detector Based Bit Sequential Pipelined Analog Multiplier for Convolutional Neural Networks (CNN) Acceleration," KCS 2021.
Seoyeong Jo, and Jaeha Kim, "A Digital Phase-Locked Loop with Finite Impulse Response," IEIE Summer Conference, 2020.
Joonho Park and Jaeha Kim, "Design of Low-Loss, High-Efficiency Step-Up Hybrid Switched-Capacitor Converter for IoT Smart Nodes," KCS 2020.
Wooryeol Kim and Jaeha Kim, "A Two-Step Coarse-Fine Time-to-Digital Conversion Technique Using Oscillation Collapse-Based Ring Oscillator," KCS 2020.
Chan Young Park and Jaeha Kim, "An Event-Driven Simulation Methodology for Boost-type Battery Charger IC With Frequency-Sweeping Input Voltage Monitor," KCS 2020.
Youngjun Kim and Jaeha Kim, "Charge Matching Digital Gate Model for Event Driven Simulation of Circuit with Power Delivery Network," KCS 2019.
Se-won Kim, Youngjun Kim, and Jaeha Kim, "Gain Control Method for Fast Locking Bang-Bang Phase-Locked Loop", KCS 2019.
Jiyeon Lee and Jaeha Kim, "Method of Detecting Voltage Drop at Power Distribution Networks with Simple Matrix Calculations", KCS 2019.
Jiho Lee and Jaeha Kim, "Estimating Performance Trade-off between Supply-Induced Jitter and Power Consumption of Clock Distribution Path for Memory I/O Block", KCS 2019.
Sung-Joon Lee and Jaeha Kim, "A 0.9-mW 2-GHz Programmable Integer-N Synchronous Frequency Divider with 50% Duty-Cycle Output for PLL Application," 한국반도체학술대회, 2017년 2월
Jieun Jang and Jaeha Kim, "Event-Driven Simulation of Input-Dependent Nonlinear Behaviors," 2015년 한국반도체학술대회 (KCS)
Seuk Son and Jaeha Kim, "A Noise-Resilient and Ditherless Lock Detection Scheme for Bang-Bang Controlled Calibration Loops," 2015년 한국반도체학술대회 (KCS)
Jiho Lee and Jaeha Kim, "Analysis of Characterizing Feasible Design Space of LC-VCO Using SVM Classifiers," 2015년 한국반도체학술대회 (KCS)
Sung-Joon Lee and Jaeha Kim, "A 256-Radix Crossbar Switch using Mux-Matrix-Mux Folded-Clos Topology," 한국반도체학술대회, 2014년 2월.
백승헌, 김재하, "HyperX 구조를 이용한 저전력 256-Radix Crossbar Switch의 설계," 한국반도체학술대회, 2014년 2월.
김준석, 장지은, 김재하, "Accurate Frequency Spectrum Analysis of Event-Driven Simulation Results of Analog/Mixed-Signal Circuits," 한국반도체학술대회, 2014년 2월.
여환석, 류시강, 최윤주, 김재하, "PVT-Insensitive, Adaptive-Bandwidth Digital PLL Design with Constant Relative-Gain DCO," 한국전자파학회 하계종합학술대회, 2013년 8월.
류시강, 여환석, 최윤주, 김재하, "A Calibration-Free Two-Point Modulation Technique for High Data Rate Polar RF Transmitter," 한국전자파학회 하계종합학술대회, 2013년 8월.
강태욱, 김재하, "Class-D 증폭기 구조를 이용한 에너지 회수형 게이트 드라이버 회로", 대한전자공학회 추계학술대회, 2012년 11월.
최윤주, 정서빈, 김재하, "A 5-Bit, Constant Relative-Gain Digitally Controlled Oscillator for All-Digital, Adaptive-Bandwidth PLL/CDRs" SoC 학술대회, 2012년 5월.
류시강, 김재하, "An Integration-Based, Spread-Spectrum-Clocking Tracking Aid for Digital Clock and Data Recovery Loops" 한국반도체학술대회, 2012년 2월.
한용수, 신보경, 김재하, "Design of Low-Jitter, Low-Power Clock Distribution Network with Inductive Peaking," 한국반도체학술대회, 2011년 2월.
김한석, 최윤주, 김수지, 김재하, "Silicon Odometer Exploiting Electromigration," 한국반도체학술대회, 2011년 2월.
이민복, 김재하, "Optimization of On-chip Inductors for Fully-Monolithic Buck Converter," 한국반도체학술대회, 2011년 2월.
최윤주, 김수지, 김한석, 김재하, "Maximum-Likelihood Detection Method for Robust Chip-ID generation Using Comparator Mismatch," 한국반도체학술대회, 2011년 2월.
강태욱, 김재하, "Class-D 증폭기 구조를 이용한 에너지 회수형 게이트 드라이버 회로", 대한전자공학회 추계학술대회, 2012년 11월.
최윤주, 정서빈, 김재하, "A 5-Bit, Constant Relative-Gain Digitally Controlled Oscillator for All-Digital, Adaptive-Bandwidth PLL/CDRs" SoC 학술대회, 2012년 5월.
류시강, 김재하, "An Integration-Based, Spread-Spectrum-Clocking Tracking Aid for Digital Clock and Data Recovery Loops" 한국반도체학술대회, 2012년 2월.
한용수, 신보경, 김재하, "Design of Low-Jitter, Low-Power Clock Distribution Network with Inductive Peaking," 한국반도체학술대회, 2011년 2월.
김한석, 최윤주, 김수지, 김재하, "Silicon Odometer Exploiting Electromigration," 한국반도체학술대회, 2011년 2월.
이민복, 김재하, "Optimization of On-chip Inductors for Fully-Monolithic Buck Converter," 한국반도체학술대회, 2011년 2월.
최윤주, 김수지, 김한석, 김재하, "Maximum-Likelihood Detection Method for Robust Chip-ID generation Using Comparator Mismatch," 한국반도체학술대회, 2011년 2월.

Invited Talks and Lectures

J. Kim, "Clocking Techniques for Dynamic Frequency Scaling", International Solid-State Circuits Conference, California, USA, Feb, 17, 2013.
J. Kim, "Analog Design Automation: Is It A Dream?", Invited Lecture at 2012 Analog and Power IC Workshop, Seoul, Korea, April 27, 2012.
J. Kim, "Three Big Problems for IC Scaling: Bandwidth, Power, and Design Complexity", 2011 Rambus Design Seminar (RDS Korea), Seoul, Korea, December 8, 2011.
J. Kim, "Power-Supply on Chip (PowerSoC): Trends and Challenges", Invited Keynote at 2011 Dongbu-HiTek Analog IC Design Contest Award Ceremony, Seoul, Korea, April 6, 2011.
J. Kim, "What Designers Want – Myths and Fallacies of Analog Circuit Optimizers," talk given at BK21 Semi-annual Workshop Between Seoul National University and University of Michigan, Ann Arbor, Seoul, Korea, August 19, 2010.
J. Kim, “Mixed-Signal System Verification: A High‐Speed Link Example”, Invited tutorial given at Int’l Conf. on Computer Aided Verification (CAV), Grenoble, France, June 28, 2009.
J. Kim, “Design Considerations for 40‐Gbps Serial Transceiver in CMOS,” Keynote speech given at 1st Asian‐Pacific Solid‐State Circuit Workshop, Seoul, Korea, Aug. 22, 2008.
J. Kim, “The Forgotten Art of Linear Analysis,” Invited tutorial on robust analog design, Design Automation Conf., Anaheim, CA, U.S.A., June 13, 2008.
J. Kim, “Design Verification Challenges in Mixed‐Signal Systems,” Invited talk at Designers’ Perspectives track, Int’l Conf. on Computer Aided Design, San Jose, CA, U.S.A., Nov. 7, 2006.
J. Kim, “Design Principles of High‐Speed Serial Interface,” Short courses at National Chiao‐Tung University, Hsinchu, and National Taiwan University, Taipei, Taiwan, Oct. 14‐15, 2004.
J. Kim and V. Stojanovic, “Performance Estimation of High‐Speed Backplane Interconnects,” Short course on High‐speed Interfaces, Symp. on VLSI Circuits, Honolulu, HI, U.S.A., June 16, 2004.
J. Kim, “Design of CMOS Adaptive‐Bandwidth PLL/DLLs,” Invited tutorial at Samsung Electronics, Inc., Hwasung, Kyunggi‐Do, Korea, May 2004.

Book Chapters

D. Harris, J. Kim, "Chapter 13. Special-Purpose Subsystems," CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Addison-Wesley, 2010.
G.‐Y. Wei, M. A. Horowitz and J. Kim, “Energy‐efficient Design of High‐Speed Links,” Power Aware Design Methodologies (edited by M. Pedram and J. Rabaey), Kluwer Academic Publishers, Contributed Chapter, June 2002.

Patents

International

J. Kim, H. Yeo, S. Ryu, “Synthesizing Method of Signal Having Variable Frequency and Synthesizer of Signal Having Variable Frequency,” US Patent App. 2014/604533, filed Jan. 2015.
J. Kim, B. Haukness, “Clock Generator Circuits with Non‐volatile Memory for Storing and/or Feedback Controlling Phase and Frequency,” WIPO Patent App. 2009/026513, filed Aug. 2008.
Y. Frans, H. Lee, J. Kim, “Injection‐Locked Clock Multiplier,” WIPO Patent App. 2008/144152, filed Apr. 2008.
H. Lee, J. Kim, B. Leibowitz, “Integrated Circuit Having Receiver Jitter Tolerance (‘JTOL’) Measurement,” WIPO Patent App. 2008/115968, filed Mar. 2008.
J. Kim, H. Lee, T. H. Greer III, “Hardware and Method to Test Phase Linearity of Phase Synthesizer,” WIPO Patent App. 2008/118659, filed Mar. 2008.
J. Kim, H. Lee, J.‐H. Chun, J. Zerbe, “Methods and Systems for Transmitting Auxiliary Data by Modulating Pre‐emphasis Filter Coefficients,” WIPO Patent App. 2008/150321, filed Mar. 2008.
J. Kim, K. D. Jones, M. A. Horowitz, “Transforming Variable Domains for Linear Circuit Analysis,” WIPO Patent App. 2008/127793, filed Feb. 2008.
J. Kim, M. A. Horowitz, K. D. Jones, “Noise Model Method of Predicting Mismatch Effects on Transient Circuit Behaviors,” WIPO Patent App. 2008/109337, filed Feb. 2008.
J. L. Zerbe, J. Kim, Y. Frans, H. M. Nguyen, “Optimized Power Supply for an Electronic System,” WIPO Patent App. 2008/109341, filed Feb. 2008.
J. Kim, D.‐K. Jeong, “Adaptive Bandwidth Phase‐locked Loop with Feedforward Divider,” US Patent App. 11637254, filed Dec. 2006.
J. G. Maneatis, J. Kim, D. K. Hartman, “Delay‐locked Loop with Dynamically Biased Charge Pump,” US Patent App. 11347835, filed Feb. 2006.
W. J. Choe, D.‐K. Jeong, J. Kim, B.‐J. Lee, M.‐K. Kim, “Clock‐edge Modulated Serial Link with DC‐balance Control,” US Patent App. 11264303, filed Oct. 2005.

Domestic

김재하, 여환석, 류시강, "가변 주파수 신호 합성 방법 및 이를 이용한 가변 주파수 신호 합성기", 출원번호 10-2014-0009207, 2014년 1월 24일.
김재하, 강은철, "LED 드라이버", 출원번호 10-2011-0032886, 2011년 4월 8일.
김재하, 강은철, "역률 향상을 위한 LED 드라이버", 출원번호 10-2011-0032885, 2011년 4월 8일.