About Hwanseok Yeo

Biography

Hwanseok Yeo is currently working toward the Ph.D. degree in electrical engineering at Seoul National University and his research interests include low-power mixed-signal systems and their design methodologies. He received B.S. and M.S. degrees in electrical engineering from Sogang University in 2003 and 2005 respectively. From 2005 to 2011, he was a principle engineer with Samsung Electronics, Korea, working on PLL/DLL designs for high-speed interfaces, LCD timing controllers and mobile application processors.

Contact Information
- Email: hsyeo@mics.snu.ac.kr

Research Interests

High-Performance PLL/CDR Design Using Digital Techniques
And Their Related Circuits and Issues

Publications

Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," International Solid-State Circuits Conference (ISSCC), 2016.
J. Kim, H. Yeo, S. Ryu, “Synthesizing Method of Signal Having Variable Frequency and Synthesizer of Signal Having Variable Frequency,” US Patent App. 2014/604533, filed Jan. 2015.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, and Jaeha Kim "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function" IEEE Jounal of Solid-State Circuits (JSSC), Aug. 2014.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," Custom Integrated Circuits Conference (CICC), Sep. 2013.
Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," Symposium of VLSI Circuits, 2013.
여환석, 류시강, 최윤주, 김재하, "PVT-Insensitive, Adaptive-Bandwidth Digital PLL Design with Constant Relative-Gain DCO," 한국전자파학회 하계종합학술대회, 2013년.

My Research Projects

Wideband Chirping All-Digital Frequency Synthesizer
Multiphase PLL with a Fractionally Injection-Locked Ring Oscillator to an LC VCO
Wide-range LC-PLL with fractional divider

Deletions are marked like this.	Additions are marked like this.
Line 29:	Line 29:
Email: hsyeo@mics.snu.ac.kr