About hsyeo

Biography

Hwanseok Yeo is currently working toward the Ph.D. degree in electrical engineering at Seoul National University and his research interests include low-power mixed-signal systems and their design methodologies. He received B.S. and M.S. degrees in electrical engineering from Sogang University in 2003 and 2005 respectively. From 2005 to 2011, he was a design engineer with Samsung Electronics, Korea, working on PLL/DLL designs for high-speed interfaces, LCD timing controllers and mobile application processors.

Contact Information

- Email: <hsyeo AT mics.snu.ac.kr>'

Research Interests

High-Performance PLL/CDR Design Using Digital Techniques
And Their Related Circuits and Issues

Publications

Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," International Solid-State Circuits Conference (ISSCC), 2016.
J. Kim, H. Yeo, S. Ryu, “Synthesizing Method of Signal Having Variable Frequency and Synthesizer of Signal Having Variable Frequency,” US Patent App. 2014/604533, filed Jan. 2015.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, and Jaeha Kim "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function" IEEE Jounal of Solid-State Circuits (JSSC), Aug. 2014.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," Custom Integrated Circuits Conference (CICC), Sep. 2013.

Personal Area

My Research Projects

Wideband Chirping All-Digital Frequency Synthesizer
Multiphase PLL with a Fractionally Injection-Locked Ring Oscillator to an LC VCO
Wide-range LC-PLL with fractional divider

CategoryHomepage

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* PLL with a Fractionally Injection-Locked Ring Oscillator to an LC VCO	* Multiphase PLL with a Fractionally Injection-Locked Ring Oscillator to an LC VCO