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= Publications = * Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," Custom Integrated Circuits Conference (CICC), Sep. 2013. |
Contents
About hsyeo
Biography
Hwanseok Yeo is currently working toward the Ph.D. degree in electrical engineering at Seoul National University and his research interests include low-power mixed-signal systems and their design methodologies. He received B.S. and M.S. degrees in electrical engineering from Sogang University in 2003 and 2005 respectively. From 2005 to 2011, he was a design engineer with Samsung Electronics, Korea, working on PLL/DLL designs for high-speed interfaces, LCD timing controllers and mobile application processors.
Contact Information
![[ATTACH]](/wiki/hsyeo?rename=hsyeo.jpg&action=AttachFile "[ATTACH]"){kind=small}
- Email: <hsyeo AT mics.snu.ac.kr>'
Research Interests
- High-Performance PLL/CDR Design Using Digital Techniques
- And Their Related Circuits and Issues
- All-Digital PLL-Based Transmitter
- Ultra-Fast PLL Settling and High-Speed Digitally-Controlled Oscillator (DCO)
- Wide-Bandwidth All-Digital PLL