| Deletions are marked like this. | Additions are marked like this. |
| Line 15: | Line 15: |
| * High-Performance PLL/CDR Design using Digital Techniques | * High-Performance PLL/CDR Design Using Digital Techniques |
| Line 36: | Line 36: |
|
== My Research Blogs == <<NewBlog(BlogTemplate, Create/Edit Today's Blog, @ME)>> <<MonthCalendarTopList(30)>> ## Click on the date to create or edit the blogs ||<^><<MonthCalendar(,,,0,,,,BlogTemplate)>>||<^><<MonthCalendar(,,,-1,,,,BlogTemplate)>>||<^><<MonthCalendar(,,,-2,,,,BlogTemplate)>>|| == My Calendar == <<GoogleCalendar(@ME, 1200, 900)>> == My Favorite Links == ## List your favorite links here as desired. |
Contents
About hsyeo
Biography
Hwanseok Yeo is currently working toward the Ph.D. degree in electrical engineering at Seoul National University and his research interests include low-power mixed-signal systems and their design methodologies. He received B.S. and M.S. degrees in electrical engineering from Sogang University in 2003 and 2005 respectively. From 2005 to 2011, he was a design engineer with Samsung Electronics, Korea, working on PLL/DLL designs for high-speed interfaces, LCD timing controllers and mobile application processors.
Contact Information
![[ATTACH]](/wiki/hsyeo?rename=hsyeo.jpg&action=AttachFile "[ATTACH]"){kind=small}
- Email: <hsyeo AT mics.snu.ac.kr>'
Research Interests
- High-Performance PLL/CDR Design Using Digital Techniques
- And Their Related Circuits and Issues
- All-Digital PLL-Based Transmitter
- Ultra-Fast PLL Settling and High-Speed Digitally-Controlled Oscillator (DCO)
- Wide-Bandwidth All-Digital PLL