About Yunju Choi

Biography

Yunju Choi received the B.S. and M.S. degrees in electrical engineering from Seoul National University (SNU) in 2011 and 2013, respectively. She is currently pursuing the Ph.D. degree in electrical engineering at SNU.

Contact Information
- Email: <yunju AT SPAMFREE mics DOT snu DOT ac DOT kr>

Publications

Minbok Lee, Yunju Choi, Jaeha Kim, "A 500-MHz, 0.76-W/mm2 Power Density and 76.2% Power Efficiency, Fully-Integrated Digital Buck Converter in 65nm CMOS", IEEE Trans. Industry Applications, 2016
Minbok Lee, Yunju Choi and Jaeha Kim, "A 0.76W/mm2 On-chip Fully-Integrated Buck Converter with Negatively-Coupled, Stacked-LC Filter in 65nm CMOS," Energy Conversion Congress & Expo (ECCE), 2014
Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," IEEE Symp. on VLSI Circuits, June 2013.
Yunju Choi and Jaeha Kim, "Robust Random Chip ID Generation with Wide-Aperture Clocked Comparators and Maximum Likelihood Detection," IEEE International Symposium on Circuits and Systems, May 2013.
Seobin Jung, Yunju Choi, Jaeha Kim, "Variability-Aware, Discrete Optimization for Analog Circuits," ACM/IEEE Design Automation Conference (DAC), June 2012.
Jaeha Kim, Sigang Ryu, Byoungjoo Yoo, Hanseok Kim, Yunju Choi, and Deog-Kyoon Jeong, "A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs," IEEE International Symposium on Circuits and Systems, May 2012.

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 * Minbok Lee, Yunju Choi, Jaeha Kim, "A 500-MHz, 0.76-W/mm2 Power Density and 76.2% Power Efficiency, Fully-Integrated Digital Buck Converter in 65nm CMOS", IEEE Trans. Industry Applications, 2016

 * Minbok Lee, Yunju Choi and Jaeha Kim, "A 0.76W/mm2 On-chip Fully-Integrated Buck Converter with Negatively-Coupled, Stacked-LC Filter in 65nm CMOS," Energy Conversion Congress & Expo (ECCE), 2014

 * Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," IEEE Symp. on VLSI Circuits, June 2013.

 * Yunju Choi and Jaeha Kim, "Robust Random Chip ID Generation with Wide-Aperture Clocked Comparators and Maximum Likelihood Detection," IEEE International Symposium on Circuits and Systems, May 2013.

 * Seobin Jung, Yunju Choi, Jaeha Kim, "Variability-Aware, Discrete Optimization for Analog Circuits," ACM/IEEE Design Automation Conference (DAC), June 2012.

 * Jaeha Kim, Sigang Ryu, Byoungjoo Yoo, Hanseok Kim, Yunju Choi, and Deog-Kyoon Jeong, "A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs," IEEE International Symposium on Circuits and Systems, May 2012.