About Sigang Ryu

Biography

Sigang Ryu received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 2011, and the M.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 2014. He is currently pursuing the Ph.D. degree in electrical engineering at Seoul National University. His current research interests include high-speed timing circuits (D/PLL, CDR) and their design methodologies.

Contact Information
- Email: <sgryu AT SPAMFREE mics DOT snu DOT ac DOT kr>

Research Interests

Digital PLL/DLL, CDR for high-speed link system
Serdes for high-speed serial links
Automation methodology for implementation of mixed-signal system

Publications

Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," International Solid-State Circuits Conference (ISSCC), 2016.
J. Kim, H. Yeo, S. Ryu, “Synthesizing Method of Signal Having Variable Frequency and Synthesizer of Signal Having Variable Frequency,” US Patent App. 2014/604533, filed Jan. 2015.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, and Jaeha Kim "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function" IEEE Jounal of Solid-State Circuits (JSSC), Aug. 2014.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," Custom Integrated Circuits Conference (CICC), Sep. 2013.
Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," Symposium of VLSI Circuits, 2013.
Jaeha Kim, Sigang Ryu, Byoungjoo Yoo, Hanseok Kim, Yunju Choi, and Deog-Kyoon Jeong, "A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs," IEEE International Symposium on Circuits and Systems, May 2012.

My Research Projects

Collaborative timing recovery for 4-PAM serial links
Model-first design flow (cell-based design flow)
Digital PLL implementing peaking-less transfer function
Digital PLL with sub-ps jitter using high-resolution pipelined ADC

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