Main Research Directions

• MICS Research Overview (in English)

• MICS 연구실의 연구방향 소개 (한글)

Gordon Moore, in his seminal article in 1965, made a projection that the number of transistors on a chip will increase exponentially over the years. This projection is now known as Moore’s law. In the very same paper, he also listed anticipated challenges for sustaining such phenomenal growth in the level of integration. Those included excessive power dissipation and unmanageable design complexity/cost. More than 40 years later, Moore’s concerns have come true. Those are the key challenges that IC designers are facing today.

Our overall research objective is to address these challenges with unique mixed-signal system approaches. Our research efforts can be classified into the following three categories:

• Continue on the design of energy-efficient, high-performance digital I/O interfaces through mixed-signal architectures combining both strengths of analog and digital.
• Pioneer in the area of analog/mixed-signal design and verification methodologies to facilitate efficient design and reuse despite aggressive technology scaling.
• Explore new applications where mixed-signal approaches can benefit: for instance, nano/bio/medical sensor interfaces and power electronics.

High-Performance, Low-Power Interconnects

• High-speed transceivers and serializer/deserializers
• Precise timing generation circuits (PLL/DLLs)
• Clock and data recovery loops (CDRs)

Design and Validation Methodologies for Analog and Mixed-Signal Systems

• Leveraging linear abstraction to simplify analog verification
• Intent-based design methodologies: circuit optimization, modeling, and coverage analysis
• Verifying if intent is realized properly: e.g. global convergence analysis
• Enabling robust design of mixed-signal "A+D" systems

• CircuitBook: a shared repository of analog circuit blocks

Exploring New Areas based on Our Expertise

• Systems traditionally designed based on ADC and DSP: sensor interfaces and smart power ICs
• Adopt the unique "A+D" systems in high-speed links to achieve high performance and low power
• Integrated mixed-domain systems: e.g. bio-sensors, power converters, silicon photonics, etc.

Our Research Collaborators/Sponsors

MICS Publications

Journal Publications

• J. Kim, E.-H. Chen, J. Ren, B. S. Leibowitz, P. Satarzadeh, J. L. Zerbe, C.-K. K. Yang, "Equalizer Design and Performance Trade-offs in ADC-based Serial Links," to appear in IEEE Trans. Circuits and Systems I, Sep. 2011.
• J. Kim, K. D. Jones, M. A. Horowitz, “Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch,” IEEE Trans. Circuits and Systems I, July 2010.
• J. Kim, J.‐K. Kim, B.‐J. Lee, D.‐K. Jeong, “Design Optimization of On‐chip Inductive Peaking Structures for 0.13‐um CMOS 40‐Gb/s Transmitter Circuits,” IEEE Trans. Circuits and Systems I, Dec. 2009.
• J. Kim, B. S. Leibowitz, J. Ren, C. J. Madden, “Simulation and Analysis of Random Decision Errors in Clocked Comparators,” IEEE Trans. Circuits and Systems I, Aug. 2009.
• J. Kim, “On‐Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs”, IEEE Trans. Circuits and Systems II, June 2009.
• J.‐K. Kim, J. Kim, G. Kim, D.‐K. Jeong, “A Fully Integrated 0.13‐um CMOS 40‐Gb/s Serial Link Transceiver,” IEEE J. Solid‐State Circuits, May 2009.
• J. Kim, “Adaptive‐Bandwidth Phase‐Locked Loop with Continuous Background Frequency Calibration”, IEEE Trans. Circuits and Systems II, Mar. 2009.
• M.‐S. Hwang, J. Kim, D.‐K. Jeong, “Reduction of Pump Current Mismatch in Charge‐Pump PLL,” IET Electronics Letters, Jan. 2009.
• W.‐J. Choe, B.‐J. Lee, J. Kim, D.‐K. Jeong, G. Kim, ʺA Single‐Pair Serial Link for Mobile Displays for Clock Edge Modulation Scheme,ʺ IEEE J. Solid‐State Circuits, Sep. 2007.
• J. Kim, J.‐K. Kim, B.‐J. Lee, N. Kim, D.‐K. Jeong, W. Kim, “A 20‐GHz Phase‐Locked Loop for 40Gb/s Serializing Transmitter in 0.13‐um CMOS,” IEEE J. Solid‐State Circuits, Apr. 2006.
• E. Alon, J. Kim, S. Pamarti, K. Chang, M. Horowitz ʺReplica Compensated Linear Regulators for Supply‐Regulated Phase‐Locked Loops,ʺ IEEE J. Solid‐State Circuits, Feb. 2006.
• H.‐R. Lee, M.‐S. Hwang, B.‐J. Lee, Y.‐D. Kim, D. Oh, J. Kim, S.‐H. Lee, D.‐K. Jeong, W. Kim, “A 1.2V‐only 900‐mW 10Gb Ethernet Transceiver and XAUI Interface with Robust VCO Tuning Technique,” IEEE J. Solid‐State Circuits, Nov. 2005.
• J. Kim and D.‐K. Jeong, “Multi‐gigabit‐rate Clock and Data Recovery Based on Blind Oversampling,” IEEE Communication Magazine, Dec. 2003.
• J. Kim, M. A. Horowitz, and G.‐Y. Wei, “Design of CMOS Adaptive‐bandwidth PLL/DLLs: A General Approach,” IEEE Trans. Circuits and Systems II, Nov. 2003.

• J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, M. Shankaradas, “Self‐Biased, High‐Bandwidth, Low‐Jitter 1‐to‐4096 Multiplier Clock‐Generator PLL,” IEEE J. Solid‐State Circuits, Nov. 2003.

• J. Kim and M. A. Horowitz, “Adaptive Supply Serial Links with Sub‐1V Operation and Per-pin Clock Recovery,” IEEE J. Solid‐State Circuits, Nov. 2002.
• J. Kim and M. A. Horowitz, “An Efficient Digital Sliding Controller for Adaptive Power Supply Regulation,” IEEE J. Solid‐State Circuits, May 2002.
• G.‐Y. Wei, J. Kim, D. Liu, S. Sidiropoulos, M. Horowitz, “A Variable‐Frequency Parallel I/O Interface with Adaptive Power‐Supply Regulation,” IEEE J. Solid‐State Circuits, Nov. 2000.

Conference Publications

International

• Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyung Hoon Kim, and Jaeha Kim, "A 2.3-mW, 5-Gb/s Decision-Feedback Equalizing Receiver Front-End with Static-Power-Free Signal Summation and CDR-based Precursor ISI Reduction," IEEE Asian Solid-State Circuits Conference 2012
• Kyung Hoon Kim, Jaeha Kim, "Fault Coverage Analysis on Analog/Mixed-Signal Circuits Based on Statistical Dissimilarity," poster session in IEEE Int’ Test Conf., Nov 201
• Jihyun Ryoo, Seuk Son, and Jaeha Kim, "A 25–FO4, 81-mW Radix-64 Crossbar Switch with Partially-Activated Input and Output Lines," International SoC Design Conference 2012
• Ji-Eun Jang, Myeong-Jae Park, Dongyun Lee and Jaeha Kim "True Event-Driven Simulation of Analog/Mixed-Signal Behaviors in System Verilog: A Decision-Feedback Equalizing (DFE) Receiver Example," IEEE Custom Integrated Circuits Conference, Sep, 2012.
• Myeong-Jae Park, Hanseok Kim, Seuk Son and Jaeha Kim "A 5-Gbps 1.7pJ/bit Ditherless CDR with Optimal Phase Interval Detection," IEEE Custom Integrated Circuits Conference, Sep. 2012.
• Seobin Jung, Yunju Choi, Jaeha Kim, "Variability-Aware, Discrete Optimization for Analog Circuits," ACM/IEEE Design Automation Conference, June 2012.
• Jaeha Kim, Sigang Ryu, Byoungjoo Yoo, Hanseok Kim, Yunju Choi, and Deog-Kyoon Jeong, "A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs," IEEE International Symposium on Circuits and Systems, May 2012.
• Eunchul Kang and Jaeha Kim, "A Single-Stage Off-line LED Driver IC with Hysteric Power Factor Correction Control," Applied Power Electronics Conference and Exposition (APEC), Feb. 2012.
• Myeong-Jae Park, Hanseok Kim, Minbok Lee, Jaeha Kim, "Fast and Accurate Event-Driven Simulation of Mixed-Signal Systems with Data Supplementation," IEEE Custom Integrated Circuits Conference, Sep. 2011.
• Kyunghoon Kim, Jaeha Kim, "Investigations on the Use of Negative-Resistance Terminations for Multi-Drop Bus Channels," IEEE International Midwest Symposium on Circuits and Systems, Aug. 2011.
• Seobin Jung, Sangho Youn, Jaeha Kim, "Analysis on Performance Controllability under Process Variability: A Step Towards Grid-Based Analog Circuit Optimizers", Frontiers in Analog Circuit (FAC) Synthesis and Verification, July 2011.
• Sangho Youn, Jaeha Kim, Mark Horowitz, "Preventing Global Convergence Failures in Mixed-Signal Systems by Eliminating Indeterminate States", Frontiers in Analog Circuit (FAC) Synthesis and Verification, July 2011.
• Eunchul Kang, Jaeha Kim, Dohwan Oh, Dongjin Min, "A 6.8-W Purely-Resistive AC Light-Emitting Diode Driver Circuit with 95% Power Factor", International Conference on Power Electronics, May 2011.
• S. Youn, J. Kim, M. A. Horowitz, "Global Convergence Analysis of Mixed-Signal Systems", ACM/IEEE Design Automation Conf. (DAC), June 2011.
• J. Kim, J. Ren, B. S. Leibowitz, P. Satarzadeh, A. Abbasfar, J. Zerbe, "Equalizer Design and Performance Trade-offs in ADC-based Serial Links," Custom Integrated Circuits Conference (CICC), Sept. 2010.
• B. C. Lim, J. Kim, M. A. Horowitz, "An Efficient Test Vector Generation for Checking Analog/Mixed-Signal Functional Models", ACM/IEEE Design Automation Conf. (DAC), June 2010.

• M. Jeeradit, J. Kim, M. Horowitz, "Intent-leveraged Optimization of Analog Circuits via Homotopy," Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2010.

• J. Kim, M. Jeeradit, B. Lim, M. A. Horowitz, "Leveraging Designer’s Intent: A Path Toward Simpler Analog CAD Tools", Custom Integrated Circuits Conference (CICC), 2009.
• J. Kim, J. Ren, M. A. Horowitz, “Stochastic Steady‐State and AC Analyses of Mixed‐Signal Systems,” ACM/IEEE Design Automation Conf. (DAC), July 2009.
• J. Kim, M. Jeeradit, A. Varzaghani, I. Huang, “A Schematic Symbol Library for Collaborative Analog Circuit Development Across Multiple Process Technologies,” ACM/IEEE Design Automation Conf. (DAC), Users Track, July 2009.
• J. Kim, B. S. Leibowitz, M. Jeeradit, “Impulse Sensitivity Function Analysis of Periodic Circuits,” ACM/IEEE Int’l Conf. on Computer‐Aided Design (ICCAD), Nov. 2008.
• J.‐K. Kim, J. Kim, D.‐K. Jeong, “A 20‐Gb/s Full‐Rate 27‐1 PRBS Generator Integrated with 20‐GHz PLL in 0.13‐m CMOS,” IEEE Asian Solid‐State Circuits Conf., Nov. 2008.
• B. S. Leibowitz, J. Kim, J. Ren, C. Madden, “Characterization of Random Decision Errors in Clocked Comparators,” IEEE Custom Integrated Circuits Conference (CICC), Sep. 2008.
• M. Jeeradit, J. Kim, B. S. Leibowitz, P. Nikaeen, V. Wang, B. Garlepp, C. Werner, ʺCharacterizing Sampling Aperture of Clocked Comparators,ʺ IEEE Symp. on VLSI Circuits, June 2008.
• J.‐K. Kim, J. Kim, G. Kim, D.‐K. Jeong, ʺA 40Gb/s Transceiver in 0.13m CMOS Technology,ʺ IEEE Symp. on VLSI Circuits, June 2008.
• K. D. Jones, J. Kim, V. Konrad, “Some ‘Real World’ Problems in Analog and Mixed‐Signal Domains,” Designing Correct Circuits, Mar. 2008.
• J. Kim, K. D. Jones, M. A. Horowitz, ʺVariable Domain Transformation for Linear PAC Analysis of Mixed‐Signal Systems,ʺ ACM/IEEE Int’l Conf. on Computer‐Aided Design (ICCAD), Nov. 2007.
• J.‐K. Kim, J. Kim, S.‐Y. Lee, S. Kim, D.‐K. Jeong, ʺA 26.5‐37.5 GHz Frequency Divider and a 73‐GHz‐BW CML Buffer in 0.l3-um CMOS,ʺ IEEE Asian Solid‐State Circuits Conf., Nov. 2007.
• J. Kim, K. D. Jones, M. A. Horowitz, ʺFast, Non‐Monte‐Carlo Estimation of Transient Performance Variation Due to Device Mismatch,ʺ ACM/IEEE Design Automation Conf. (DAC), June 2007.
• S.‐Y. Lee, J. Kim, B.‐J. Lee, H.‐C. Kim, H.‐H. Ko, D. Dan Cho, D.‐K. Jeong, ʺA Bandpass Sigma‐Delta Interface IC for Sacrificial Bulk Micromachined Inertial Sensors,ʺ IEEE Asian Solid‐State Circuits Conf., Nov. 2006.
• J. Kim, J.‐K. Kim, B.‐J. Lee, N. Kim, D.‐K. Jeong, and W. Kim, “A 20‐GHz Phase‐Locked Loop for 40Gb/s Serializing Transmitter in 0.13um CMOS,” IEEE Symp. on VLSI Circuits, June 2005.
• B.‐J. Lee, M.‐S. Hwang, J. Kim, D.‐K. Jeong, and W. Kim, “A Quad 3.125Gbps Transceiver Cell with All‐Digital Data Recovery Circuits,” IEEE Symp. on VLSI Circuits, June 2005.
• J. Kim, J.‐K. Kim, B.‐J. Lee, M.‐S. Hwang, H.‐R. Lee, S.‐H. Lee, N. Kim, D.‐K. Jeong, and W. Kim, “Circuit Techniques for a 40Gb/s Transmitter in 0.13-m CMOS,” IEEE Int’l Solid‐State Circuits Conf. (ISSCC), Feb. 2005.
• H.‐R. Lee, M.‐S. Hwang, B.‐J. Lee, Y.‐D. Kim, D. Oh, J. Kim, S.‐H. Lee, D.‐K. Jeong, W. Kim, “A Fully Integrated 0.13-um CMOS 10Gb Ethernet Transceiver with XAUI Interface,” IEEE Int’l Solid‐State Circuits Conf. (ISSCC), Feb. 2004.

• J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, M. Shankaradas, “Self‐Biased, High‐Bandwidth, Low‐Jitter 1‐to‐4096 Multiplier Clock‐Generator PLL,” ACM/IEEE Design Automation Conference (DAC), Jun. 2003.

• J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, M. Shankaradas, “Self‐Biased, High‐Bandwidth, Low‐Jitter 1‐to‐4096 Multiplier Clock‐Generator PLL,” IEEE Int’l Solid‐State Circuits Conf. (ISSCC), Feb. 2003.

• J. Kim, M. A. Horowitz, “Adaptive Supply Serial Links with Sub‐1V Operation and Per‐pin Clock Recovery,” IEEE Int’l Solid‐State Circuits Conf (ISSCC), Feb. 2002.
• J. Kim, M. A. Horowitz, “An Efficient Digital Sliding Controller for Adaptive Power‐Supply Regulation,” IEEE Symp. on VLSI Circuits, Jun. 2001.
• S. Sidiropoulos, D. Liu, J. Kim, G.‐Y. Wei, M. Horowitz, “Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers,” IEEE Symp. on VLSI Circuits, Jun. 2000.
• G.‐Y. Wei, J. Kim, D. Liu, S. Sidiropoulos, M. Horowitz, “A Variable‐Frequency Parallel I/O Interface with Adaptive Power‐Supply Regulation,” IEEE Int’l Solid‐State Circuits Conf. (ISSCC), Feb. 2000.

Domestic

• 최윤주, 정서빈, 김재하, "A 5-Bit, Constant Relative-Gain Digitally Controlled Oscillator for All-Digital, Adaptive-Bandwidth PLL/CDRs" SoC 학술대회, 2012년 5월.
• 류시강, 김재하, "An Integration-Based, Spread-Spectrum-Clocking Tracking Aid for Digital Clock and Data Recovery Loops" 한국반도체학술대회, 2012년 2월.
• 한용수, 신보경, 김재하, "Design of Low-Jitter, Low-Power Clock Distribution Network with Inductive Peaking," 한국반도체학술대회, 2011년 2월.
• 김한석, 최윤주, 김수지, 김재하, "Silicon Odometer Exploiting Electromigration," 한국반도체학술대회, 2011년 2월.
• 이민복, 김재하, "Optimization of On-chip Inductors for Fully-Monolithic Buck Converter," 한국반도체학술대회, 2011년 2월.
• 최윤주, 김수지, 김한석, 김재하, "Maximum-Likelihood Detection Method for Robust Chip-ID generation Using Comparator Mismatch," 한국반도체학술대회, 2011년 2월.

Invited Talks and Lectures

• J. Kim, "Analog Design Automation: Is It A Dream?", Invited Lecture at 2012 Analog and Power IC Workshop, Seoul, Korea, April 27, 2012.
• J. Kim, "Three Big Problems for IC Scaling: Bandwidth, Power, and Design Complexity", 2011 Rambus Design Seminar (RDS Korea), Seoul, Korea, December 8, 2011.

• J. Kim, "Power-Supply on Chip (PowerSoC): Trends and Challenges", Invited Keynote at 2011 Dongbu-HiTek Analog IC Design Contest Award Ceremony, Seoul, Korea, April 6, 2011.

• J. Kim, "What Designers Want – Myths and Fallacies of Analog Circuit Optimizers," talk given at BK21 Semi-annual Workshop Between Seoul National University and University of Michigan, Ann Arbor, Seoul, Korea, August 19, 2010.
• J. Kim, “Mixed-Signal System Verification: A High‐Speed Link Example”, Invited tutorial given at Int’l Conf. on Computer Aided Verification (CAV), Grenoble, France, June 28, 2009.
• J. Kim, “Design Considerations for 40‐Gbps Serial Transceiver in CMOS,” Keynote speech given at 1st Asian‐Pacific Solid‐State Circuit Workshop, Seoul, Korea, Aug. 22, 2008.
• J. Kim, “The Forgotten Art of Linear Analysis,” Invited tutorial on robust analog design, Design Automation Conf., Anaheim, CA, U.S.A., June 13, 2008.
• J. Kim, “Design Verification Challenges in Mixed‐Signal Systems,” Invited talk at Designers’ Perspectives track, Int’l Conf. on Computer Aided Design, San Jose, CA, U.S.A., Nov. 7, 2006.
• J. Kim, “Design Principles of High‐Speed Serial Interface,” Short courses at National Chiao‐Tung University, Hsinchu, and National Taiwan University, Taipei, Taiwan, Oct. 14‐15, 2004.
• J. Kim and V. Stojanovic, “Performance Estimation of High‐Speed Backplane Interconnects,” Short course on High‐speed Interfaces, Symp. on VLSI Circuits, Honolulu, HI, U.S.A., June 16, 2004.
• J. Kim, “Design of CMOS Adaptive‐Bandwidth PLL/DLLs,” Invited tutorial at Samsung Electronics, Inc., Hwasung, Kyunggi‐Do, Korea, May 2004.

Book Chapters

• D. Harris, J. Kim, "Chapter 13. Special-Purpose Subsystems," CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Addison-Wesley, 2010.
• G.‐Y. Wei, M. A. Horowitz and J. Kim, “Energy‐efficient Design of High‐Speed Links,” Power Aware Design Methodologies (edited by M. Pedram and J. Rabaey), Kluwer Academic Publishers, Contributed Chapter, June 2002.

Patents

International

• J. Kim, B. Haukness, “Clock Generator Circuits with Non‐volatile Memory for Storing and/or Feedback Controlling Phase and Frequency,” WIPO Patent App. 2009/026513, filed Aug. 2008.
• Y. Frans, H. Lee, J. Kim, “Injection‐Locked Clock Multiplier,” WIPO Patent App. 2008/144152, filed Apr. 2008.
• H. Lee, J. Kim, B. Leibowitz, “Integrated Circuit Having Receiver Jitter Tolerance (‘JTOL’) Measurement,” WIPO Patent App. 2008/115968, filed Mar. 2008.
• J. Kim, H. Lee, T. H. Greer III, “Hardware and Method to Test Phase Linearity of Phase Synthesizer,” WIPO Patent App. 2008/118659, filed Mar. 2008.
• J. Kim, H. Lee, J.‐H. Chun, J. Zerbe, “Methods and Systems for Transmitting Auxiliary Data by Modulating Pre‐emphasis Filter Coefficients,” WIPO Patent App. 2008/150321, filed Mar. 2008.
• J. Kim, K. D. Jones, M. A. Horowitz, “Transforming Variable Domains for Linear Circuit Analysis,” WIPO Patent App. 2008/127793, filed Feb. 2008.
• J. Kim, M. A. Horowitz, K. D. Jones, “Noise Model Method of Predicting Mismatch Effects on Transient Circuit Behaviors,” WIPO Patent App. 2008/109337, filed Feb. 2008.
• J. L. Zerbe, J. Kim, Y. Frans, H. M. Nguyen, “Optimized Power Supply for an Electronic System,” WIPO Patent App. 2008/109341, filed Feb. 2008.
• J. Kim, D.‐K. Jeong, “Adaptive Bandwidth Phase‐locked Loop with Feedforward Divider,” US Patent App. 11637254, filed Dec. 2006.
• J. G. Maneatis, J. Kim, D. K. Hartman, “Delay‐locked Loop with Dynamically Biased Charge Pump,” US Patent App. 11347835, filed Feb. 2006.
• W. J. Choe, D.‐K. Jeong, J. Kim, B.‐J. Lee, M.‐K. Kim, “Clock‐edge Modulated Serial Link with DC‐balance Control,” US Patent App. 11264303, filed Oct. 2005.

Domestic

• 김재하, 강은철, "LED 드라이버", 출원번호 10-2011-0032886, 2011년 4월 8일.
• 김재하, 강은철, "역률 향상을 위한 LED 드라이버", 출원번호 10-2011-0032885, 2011년 4월 8일.