Contents
Purpose[edit]
Testbench for CML DC operation
Testbench for CML DC operation
Testbench for CML DC operation
Description[edit]
measuring 1)gm/ID
measuring 1)gm/ID
measuring 1)gm/ID
Outputs[edit]
Output voltage diff / Overdrive voltage of Input / Overdirve voltage of bias
Output voltage diff / Overdrive voltage of Input / Overdirve voltage of bias
Output voltage diff / Overdrive voltage of Input / Overdirve voltage of bias
Plots[edit]
Graph Name |
Filename |
Description |
vdd - vout |
vdd_v_vdiffo.png |
Measure the single output |
vdd - vov |
vdd_v_vov.png |
Measure cin transistor Vov |
Graph Name |
Filename |
Description |
vdd - vout |
vdd_v_vdiffo.png |
Measure the single output |
vdd - vov |
vdd_v_vov.png |
Measure cin transistor Vov |
Graph Name |
Filename |
Description |
vdd - vout |
vdd_v_vdiffo.png |
Measure the single output |
vdd - vov |
vdd_v_vov.png |
Measure cin transistor Vov |
load3_vdd - vout: Measure the single output[edit]
![[ATTACH]](/wiki/Projects%20Home/Perseus/tesTx/tx_cmlunit2/cmlunit_dc_vdd.py?rename=load3_vdd_v_vdiffo.png&action=AttachFile "[ATTACH]"){kind=small}
-- jhlee 2013-05-27 13:12:49
load3_vdd - vov: Measure cin transistor Vov[edit]
![[ATTACH]](/wiki/Projects%20Home/Perseus/tesTx/tx_cmlunit2/cmlunit_dc_vdd.py?rename=load3_vdd_v_vov.png&action=AttachFile "[ATTACH]"){kind=small}
-- jhlee 2013-05-27 13:12:49
load3_vdd - vout: Measure the single output[edit]
-- jhlee 2013-05-27 13:31:52
load3_vdd - vov: Measure cin transistor Vov[edit]
-- jhlee 2013-05-27 13:31:52
load3pex_vdd - vout: Measure the single output[edit]
![[ATTACH]](/wiki/Projects%20Home/Perseus/tesTx/tx_cmlunit2/cmlunit_dc_vdd.py?rename=load3pex_vdd_v_vdiffo.png&action=AttachFile "[ATTACH]"){kind=small}
-- jhlee 2013-05-27 13:42:18
load3pex_vdd - vov: Measure cin transistor Vov[edit]
![[ATTACH]](/wiki/Projects%20Home/Perseus/tesTx/tx_cmlunit2/cmlunit_dc_vdd.py?rename=load3pex_vdd_v_vov.png&action=AttachFile "[ATTACH]"){kind=small}
-- jhlee 2013-05-27 13:42:18