IC Design and Verification Tools Developed by MICS

XMODEL: A Fast Behavioral Simulator for Analog/Mixed-Signal Systems

XMODEL is an extension to SystemVerilog simulators including Synopsys VCS, MentorGraphics ModelSim and Cadence NC-Verilog that enables accurate functional modeling and fast simulation of analog/mixed-signal systems. For high-speed links, XMODEL also provides powerful statistical simulation capability that can estimate extremely low bit-error rate (BER) of 10^-12 within a few minutes. For more information, please visit http://mics.snu.ac.kr/xmodel.

Verilog-A Modules for Variable Domain Transformation

Variable Domain Transformation (VDT) is a useful concept to convert a seemingly nonlinear system in one variable domain into a linear system in another one. For instance, a phase-locked loop (PLL) that takes a large-signal clock input and produces a large-signal clock output may be viewed as a strongly-nonlinear system in voltage domain, but most PLL designers want to view it as a linear system in phase domain. With VDT modules, one can perform a periodic AC analysis (PAC) in variable domains other than voltage or current, such as phase, frequency, delay, and duty-cycle in order to simulate the AC transfer function of a phase-locked loop, delay-locked loop, duty-cycle adjuster.

• Ref: J. Kim, K. D. Jones, M. A. Horowitz, ʺVariable Domain Transformation for Linear PAC Analysis of Mixed‐Signal Systems,ʺ ACM/IEEE Int’l Conf. on Computer‐Aided Design (ICCAD), Nov. 2007 (doi).

• VDT module package: vdt.tar.gz