MICS: Mixed-Signal IC and System Group at SNU

Prof. Jaeha Kim

Faculty Advisor

Biography

Jaeha Kim (S’95–M’03–SM’09) is currently Professor at Seoul National University and his research interests include low-power mixed-signal systems and their design methodologies. He received the B.S. degree in electrical engineering from Seoul National University in 1997, and received the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1999 and 2003, respectively.

Prior to joining Seoul National University in 2010, Dr. Kim was with Stanford University, CA as Acting Assistant Professor from 2009 to 2010, with Rambus, Inc., Los Altos, CA as Principal Engineer from 2006 to 2009, and with Inter-university Semiconductor Research Center (ISRC) in Seoul National University, Seoul, Korea as Post-doctoral Researcher from 2003 to 2006. From 2001 to 2003, he was with True Circuits, Inc., Los Altos, CA as Circuit Designer. In 2015, he founded Scientific Analog, Inc., an EDA company on analog/mixed-signal verification.

Dr. Kim is a recipient of the Takuo Sugano award for outstanding far-east paper at 2005 International Solid-State Circuits Conference (ISSCC) and the Low Power Design Contest Award at 2001 International Symposium on Low Power Electronics and Design (ISLPED). Also, he is cited as Top 100 Technology Leader of Korea in 2020 by the National Academy of Engineering of Korea (NAEK). He served on the technical program committees of International Solid-State Circuits Conference, Custom Integrated Circuits Conference, Design Automation Conference (DAC), International Conference on Computer Aided Design (ICCAD), and Asian Solid-State Circuit Conference (A-SSCC).

Email: jaeha AT snu DOT ac DOT kr

Phone: (primary) +82-2-880-1671 | (secondary) +82-2-880-1672

Fax: +82-2-871-3286

Office:
(primary) Bldg 104-1, Room 314, Seoul National University
(secondary) Bldg 301, Room 507, Seoul National University

Mailing Address:
Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul, 08826, KOREA

Other Links

LinkedIn Page

Hyunjung Woo

Administrative Staff

Email: woohj@mics.snu.ac.kr

Phone: 02-871-3285

MyeongJae Park

Alumni

Biography

MyeongJae Park received the B.S., M.S. and Ph.D. degrees from Seoul National University, Seoul, Korea, in 2003, 2006 and 2014, respectively.

From 2004 to 2009, he was a design engineer with Anapass, Korea, working on LCD intra-panel interfaces. He is the inventor of Adavnced Intra-Panel Interface (AiPi), an intra-panel interface standard of Samsung's flat panel TVs. During his graduate studies, he held a summer position with Rambus Inc. in 2012, working on ultra high-speed serial interface. Since September 2014, he has been a senior research engineer with SK Hynix, Icheon, Korea. His research interests include low-power mixed-signal systems, power electronics and their design methodologies.

2014- SK Hynix, Korea
2014 Ph.D. in E.E.C.S. from Seoul National University
Thesis: A Study on Ditherless CDR with Optimal Phase Detection
2006 M.S. in E.E.C.S. from Seoul National University
2004-2009 Anapass, Korea
2003 B.S. in E.E. from Seoul National University

Email: myeongjae.park@sk.com

Kyunghoon Kim (William K. Kim)

Alumni

Biography

Kyung Hoon Kim is currently working toward the Ph.D. degree in electrical engineering at Seoul National University. He received B.S. and M.S. degrees in electrical engineering from Korea University in 2000 and 2002 respectively. He joined the Hynix semiconductor inc. from 2002 to 2011. During in 10 years at Hynix, had succeed the four mass produce, and had join to develop the first DDR3 & GDDR5 group –JEDEC, and closed community. The Hynix' GDDR5 showed the best speed performance – 5Gbps - in a world. He has published 6 papers and holds more than 60 US patents. The current research area is analog & mixed circuit design for test, and high speed interface for customized memory products.

2002- SK Hynix, Korea
2018 Ph.D. in E.E.C.S. from Seoul National University
2002 M.S. in E.E. from Korea University
2000 B.S. in E.E. from Korea University

Email: kyunghoon1.kim@sk.com

Research Interests

Analog & Mixed Signal Design Verification

Mixed signal test methodology - ATPG for mixed signal circuit
Design for Test and Built In Self Test Circuit for the high speed serial link
Mass production testing methodology - High speed wafer test interface

Circuit related to DRAM

Next generation interface for the new memory architecture (TSV)
The timing circuit such as all digital delay locked loop, real time domain crossing circuit
The negative resistance termination for cancelling channel impedance mismatch in the multi-drop channel

Publications

KyungHoon Kim, Jaeha Kim, "Investigations on the Use of Negative-Resistance Terminations for Multi-Drop Bus Channels," in Proc. IEEE International Midwest Symposium on Circuits and Systems, Aug. 2011.
Kyunghoon Kim, Jaeha Kim, "Fault Coverage Analysis on Analog/Mixed-Signal Circuits Based on Statistical Dissimilarity," poster session in IEEE Int’ Test Conf., Nov. 2012.
Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," in IEEE Symp. on VLSI Circuits, Jun. 2013.

Hanseok Kim

Alumni

Biography

2015- Samsung Electronics, Korea
2012-2014 GCT Semiconductor, Korea
2012 M.S. in E.E.C.S. from Seoul National University
Thesis: A 3.2mW 10Gb/s Low-Power Decision Feedback Equalizer
2010 B.S. in E.E. from Seoul National University

Email: hanseok.kim@samsung.com

Minbok Lee

Alumni

Biography

Minbok Lee received the B.S degree in electrical engineering from Seoul National University, Seoul, Korea, in 2010. He is currently pursuing the Ph.D. degree in electrical engineering at Seoul National University. His current research interests include DC-DC converters for power management IC (PMIC), energy harvesting circuits and their design methodologies.

2021- Cirrus Logic, USA
2017-2021 Lion Semiconductor, USA
2017 Ph.D. in E.E.C.S from Seoul National University
Thesis: A Study on Energy-Efficient Inductor Current Controls for Maximum Energy Delivery in Battery-free Buck Converter
2010 B.S. in E.E. from Seoul National University

Email: minbok@mics.snu.ac.kr

Research Interests

Mixed Signal Power Management Integrated Circuits (PMIC)

Power supply on chip (PwrSoC)
Energy Harvesting System (EHS)

Publications

Minbok Lee, Joonseok Yang, Myeong-Jae Park, Sung-Youb Jung and Jaeha Kim, "Design and Analysis of Energy-Efficient Single-Pulse Piezoelectric Energy Harvester and Power Management IC for Battery-Free Wireless Remote Switch Applications," IEEE Transactions on Circuit and Systems I, 2017.
Sung-Youb Jung, Minbok Lee, Joonseok Yang and Jaeha Kim, "A 20nW-to-140mW Input Power Range, 94% Peak Efficiency Energy-Harvesting Battery Charger with Frequency-Sweeping Input Voltage Monitor and Optimal On-Time Generator," Symposium on VLSI Circuits, 2017.
Sung-Youb Jung, Myeongjae Park, Minbok Lee, Joonseok Yang and Jaeha Kim, "Time Slot Optimization Algorithm for Multisource Energy Harvesting Systems," European Solid-State Circuits Conference(ESSCIRC), 2016.
Minbok Lee and Jaeha Kim, "Design of 93% Energy Efficiency Buck-Type Capacitor Charger IC in 250nm CMOS", IEEE Transactions on Industry Applications, 2016.
Minbok Lee, Yunju Choi, Jaeha Kim, "A 500-MHz, 0.76-W/mm2 Power Density and 76.2% Power Efficiency, Fully- Integrated Digital Buck Converter in 65nm CMOS", IEEE Transactions on Industry Applications, 2016.
Geon-Tae Hwang, Joonseok Yang, Seong Ho Yang, Ho-Yong Lee, Minbok Lee, Dae Yong Park, Jae Hyun Han, Seung Jun Lee, Chang Kyu Jeong, Jaeha Kim, Kwi-Il Park, Keon Jae Lee, "A Reconfigurable Rectified Flexible Energy Harvester via Solid-State Single Crystal Grown PMN–PZT," Advanced Energy Materials, 2015.
Minbok Lee and Jaeha Kim, "Design of 93% Energy Efficiency Buck-Type Capacitor Charger IC in 250nm CMOS," ECCE-Asia, 2015.
Joonseok Yang, Minbok Lee, Myeong-Jae Park, Sung-Youb Jung and Jaeha Kim, "A 2.5-V, 160-μJ-Output Piezoelectric Energy Harvester and Power Management IC for Batteryless Wireless Switch (BWS) Applications," VLSI Circuits Symposium, 2015.
Minbok Lee, Yunju Choi and Jaeha Kim, "A 0.76W/mm2 On-chip Fully-Integrated Buck Converter with Negatively-Coupled, Stacked-LC Filter in 65nm CMOS," Energy Conversion Congress & Expo (ECCE), 2014.
Myeong-Jae Park, Hanseok Kim, Minbok Lee, Jaeha Kim, "Fast and Accurate Event-Driven Simulation of Mixed-Signal Systems with Data Supplementation," IEEE Custom Integrated Circuits Conference, 2011.
이민복, 김재하, "Optimization of On-chip Inductors for Fully-Monolithic Buck Converter," 한국반도체학술대회, 2011.

Sangho Youn

Alumni

Biography

Sangho Youn received the B.S. and M.S. degrees in electrical engineering and computer science from Seoul National University, Seoul, Korea, in 2005 and 2007, respectively. He is currently working toward the Ph.D. degree in Seoul National University. From 2007 to 2010, he was with GCT semiconductor, Inc. Seoul, Korea, developing various wireless modem ASICs. In 2012, he was a summer intern at Texas Instruments in Dallas, TX. In 2013, he was a summer intern at Intel in Hillsboro, OR. His current interests include mixed signal IC design and CAD methodologies.

2024- AMD, USA
2019-2024 Microsoft, USA
2014-2019 Intel, USA
2014 Ph.D. in E.E.C.S. from Seoul National University
Thesis: Probabilistic Validation and Computer-Aided Debugging in Analog/Mixed-Signal Systems: Pre-Silicon Global Convergence Property Checking and Post-Silicon Bug Localization
2007-2010 GCT Semiconductor, Korea
2007 M.S. in E.E.C.S. from Seoul National University
2005 B.S in E.E from Seoul National University

Email: shyoun@mics.snu.ac.kr

Publications

Sangho Youn and Jaeha Kim, "Markov Network Based Equivalence Checking in Mixed-Signal Systems," FAC, 2013.
Sangho Youn and Jaeha Kim, "Establishing Global Convergence in Mixed-Signal Systems," SRC TECHCON 2013.
Sangho Youn and Jaeha Kim, "Preventing Global Convergence Failure in Mixed-Signal Systems via Indeterminate State (‘X’) Elimination," TCAS-1, 2013.
Sangho Youn, Jaeha Kim, Mark Horowitz, "Global Convergence Analysis of Mixed-Signal Systems", Design Automation conference, 2011.
Sangho Youn, Jaeha Kim, Mark Horowitz, "Preventing Global Convergence Failures in Mixed-Signal Systems by Eliminating Indeterminate States", Frontiers in Analog Circuit (FAC) Synthesis and Verification, 2011.
Taehwan Kim, Sangho Youn, and Jaeha Kim, "Verifying Start-up Failures in Coupled Ring Oscillators in Presence of Variability Using Predictive Global Optimization," International Conference on Computer-Aided Design (ICCAD), 2013.
Seobin Jung, Sangho Youn, Jaeha Kim, "Analysis on Performance Controllability under Process Variability: A Step Towards Grid-Based Analog Circuit Optimizers", Frontiers in Analog Circuit (FAC) Synthesis and Verification, 2011.

Sigang Ryu

Alumni

Biography

Sigang Ryu received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 2011, and the M.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 2014. He is currently pursuing the Ph.D. degree in electrical engineering at Seoul National University. He was a Researcher with the Institute of New Media and Communication, Seoul National Uni- versity, from 2017 to 2018. His current research interests include high-speed timing circuits (D/PLL and CDR), SerDes, and ADC and their design methodologies.

2024- Assistant Professor, Korea Aerospace University, Korea
2021-2024 Research Engineer, Georgia Institute of Technology, USA
2019-2021 Post-Doctoral Researcher, Inter-university Semiconductor Research Center (ISRC), Seoul National University
2019 Ph.D. in E.E.C.S. from Seoul National University
2014 M.S. in E.E.C.S. from Seoul National University
Thesis: Design of Digital PLL/CDR with Advanced Digital Controller
2011 B.S. in E.E. from Korea University

Email: sgryu@kau.ac.kr

Research Interests

Digital PLL/DLL, CDR for high-speed link system
Serdes for high-speed serial links
Analog-to-digital converters
Automation methodology for implementation of mixed-signal system

Publications

Seuk Son, Sigang Ryu, Hwanseok Yeo, and Jaeha Kim, "A 2x Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery," IEEE Journal of Solid-State Circuits (JSSC), 2019.
Sigang Ryu, Seuk Son and Jaeha Kim, "An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery," IEEE Transactions on Circuits and Systems I (TCAS-I), 2019.
Seuk Son, Hwanseok Yeo, Sigang Ryu, and Jaeha Kim, "A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery," IEEE Asian Solid-State Circuits Conference (ASSCC), 2018.
Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," IEEE International Solid-State Circuits Conference (ISSCC), 2016.
Jaeha Kim, Hwanseok Yeo, Sigang Ryu, “Synthesizing Method of Signal Having Variable Frequency and Synthesizer of Signal Having Variable Frequency,” US Patent App. 2014/604533, filed Jan. 2015.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, and Jaeha Kim "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function" IEEE Journal of Solid-State Circuits (JSSC), Aug. 2014.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013.
Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," IEEE Symposium of VLSI Circuits (SoVC), 2013.
Jaeha Kim, Sigang Ryu, Byoungjoo Yoo, Hanseok Kim, Yunju Choi, and Deog-Kyoon Jeong, "A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs," IEEE International Symposium on Circuits and Systems (ISCAS), May 2012.

My Research Projects

Collaborative timing recovery for 4-PAM serial links
Model-first design flow (cell-based design flow)
Digital PLL implementing peaking-less transfer function
Digital PLL with sub-ps jitter using high-resolution pipelined ADC

Yunju Choi

Alumni

Biography

Yunju Choi received the B.S., M.S., and Ph.D. degrees in electrical engineering from Seoul National University (SNU) in 2011, 2013, 2017, respectively.

2018- Samsung Electronics, Korea
2017 Ph.D. in E.E.C.S. from Seoul National University
Thesis: Design of Field-Programmable Mixed-Signal IC with Time-Domain Configurable Analog Block
2013 M.S. in E.E.C.S. from Seoul National University
Thesis: A Design of Adaptive Bandwidth PLL Using Constant Relative Gain DCO
2011 B.S. in E.E. from Seoul National University

Email: yunju@mics.snu.ac.kr

Publications

Yunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, and Jaeha Kim, "A Field-Programmable Mixed-Signal IC with Time-Domain Configurable Analog Blocks," Symposium on VLSI Circuits, 2016.
Minbok Lee, Yunju Choi, Jaeha Kim, "A 500-MHz, 0.76-W/mm2 Power Density and 76.2% Power Efficiency, Fully-Integrated Digital Buck Converter in 65nm CMOS", IEEE Trans. Industry Applications, 2016.
Minbok Lee, Yunju Choi and Jaeha Kim, "A 0.76W/mm2 On-chip Fully-Integrated Buck Converter with Negatively-Coupled, Stacked-LC Filter in 65nm CMOS," Energy Conversion Congress & Expo (ECCE), 2014.
Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," IEEE Symp. on VLSI Circuits, June 2013.
Yunju Choi and Jaeha Kim, "Robust Random Chip ID Generation with Wide-Aperture Clocked Comparators and Maximum Likelihood Detection," IEEE International Symposium on Circuits and Systems, May 2013.
Seobin Jung, Yunju Choi, Jaeha Kim, "Variability-Aware, Discrete Optimization for Analog Circuits," ACM/IEEE Design Automation Conference (DAC), June 2012.
Jaeha Kim, Sigang Ryu, Byoungjoo Yoo, Hanseok Kim, Yunju Choi, and Deog-Kyoon Jeong, "A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs," IEEE International Symposium on Circuits and Systems, May 2012.

Taewook Kang

Alumni

Biography

2024- Assistant Professor, Sungkyunkwan University, Korea
2021-2024 Apple, USA
2021 Ph.D. in Universitiy of Michigan, USA
2013-2016 Silicon Mitus, Korea
2013 M.S. in E.E.C.S. from Seoul National University
Thesis: Designing an Optimum On-chip Inductor using Magnetic Core
2011 B.S. in E.E. from Seoul National University

Email: twkang@skku.edu

Jieun Jang

Alumni

Biography

Jieun Jang received the M.S. degree in electrical and computer engineering from University of California Santa Barbara in 2007 and is currently working toward the Ph.D. degree at Seoul National University. She was an associate researcher at Industrial Technology Research Institute in Taiwan from 2008 to 2011, where she worked on research project to develop data converters for WiMAX communication systems. Her research interests include high-speed low-power data converters and its design methodologies.

2015- Oracle, USA
2015 Ph.D. in E.E.C.S. from Seoul National University
Thesis: Event-Driven Simulation Methodology for Analog/Mixed-Signal Systems
2008-2011 ITRI, Taiwan
2007 M.S. in E.E.C.S. from UCSB
2005 M.S. in Civil Eng. from KAIST
2003 B.C. in Civil Eng. from KAIST

Email: ji.eun.jang@oracle.com

Seobin Jung

Alumni

Biography

Seobin Jung received the B.S. degree in electrical engineering and computer science from Seoul National University, Seoul, Korea, in 2011.

2018- Google, USA
2018 Ph.D. in University of California, Berkeley
2013 M.S. in E.E.C.S. from Seoul National University
Thesis: Variability-Aware Discrete Optimization for Analog Circuits
2011 B.S. in E.E from Seoul National University

Email: seobin@berkeley.edu

Research Interests

Design Exploration and Optimization of Analog and Mixed-Signal Systems
Global Convergence Analysis of Mixed-Signal Systems
Circuit Book

Publications

Seobin Jung, Yunju Choi, and Jaeha Kim, "Variability-Aware, Discrete Optimization for Analog Circuits," ACM/IEEE Design Automation Conference, June 2012.
Seobin Jung, Sangho Youn, and Jaeha Kim, "Analysis on Performance Controllability under Process Variability: A Step Towards Grid-Based Analog Circuit Optimizers", Frontiers in Analog Circuit (FAC) Synthesis and Verification, 2011.

Hwanseok Yeo

Alumni

Biography

Hwanseok Yeo received B.S. and M.S. degrees in electrical engineering from Sogang University, Seoul, Korea in 2003 and 2005, respectively. Also, he received Ph.D. degree from Seoul National University, Seoul, Korea, in 2017. From 2005 to 2011, he was a engineer with System LSI, Samsung Electronics, Korea, working on PLL, DLL designs for high-speed interfaces, LCD timing controllers and mobile application processors. Since March 2017, he has been a senior research engineer in the same company. His research interests include mixed-signal systems such as PLL, CDR, and ADC and their design methodologies.

2005- Samsung Electronics, Korea
2017 Ph.D. in E.E.C.S. from Seoul National University
Thesis: A Design of Calibration-Free Phase-Locked Loops (PLLs)
2005 M.S. in E.E. from Sogang University
2003 B.S. in E.E. from Sogang University

Email: hwanseok.yeo@samsung.com

Research Interests

High-Performance Digital PLL and CDR Design
Cell-Based Design Flow

Publications

Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," International Solid-State Circuits Conference (ISSCC), 2016.
J. Kim, H. Yeo, S. Ryu, “Synthesizing Method of Signal Having Variable Frequency and Synthesizer of Signal Having Variable Frequency,” US Patent App. 2014/604533, filed Jan. 2015.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, and Jaeha Kim "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function" IEEE Jounal of Solid-State Circuits (JSSC), Aug. 2014.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," Custom Integrated Circuits Conference (CICC), Sep. 2013.
Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," Symposium of VLSI Circuits, 2013.
여환석, 류시강, 최윤주, 김재하, "PVT-Insensitive, Adaptive-Bandwidth Digital PLL Design with Constant Relative-Gain DCO," 한국전자파학회 하계종합학술대회, 2013년.

My Research Projects

Fast Chirp Frequency Synthesizer PLL for FMCW Radar
Multiphase PLL with a hybrid injection-locking
Wide frequency range PLL with fractional divider
Adaptive-bandwidth PLL with constant relative gain DCO

Sung-Youb Jung

Alumni

Biography

Sung-Youb Jung received the B.S. degree in electrical and computer engineering from Seoul National University in 2013, and is currently pursuing towards the Ph.D. degree. His research interest includes energy harvesting IC and low-power circuit design.

2019- Samsung Electronics, Korea
2019 Ph.D. in E.E.C.S from Seoul National University
2013 B.S. in E.E. from Seoul National University

Email: syjung@mics.snu.ac.kr

Research Interests

Energy Harvesting IC (Photovoltaic, thermoelectric generator, piezoelectric, ...)
General PMIC circuits (DC-DC converter, LDO)
Low-power circuit design (Sub-Th, nanopower circuits)
Automation scripts to help building & testing chips. (python scripts to optimize circuit design, perform chip testing measurements)

Publications

Sung-Youb Jung, Minbok Lee, Joonseok Yang and Jaeha Kim, "A 20nW-to-140mW Input Power Range, 94% Peak Efficiency Energy-Harvesting Battery Charger with Frequency-Sweeping Input Voltage Monitor and Optimal On-Time Generator," Symposium on VLSI Circuits, 2017.
Sung-Youb Jung, Myeongjae Park, Minbok Lee, Joonseok Yang and Jaeha Kim, "Time Slot Optimization Algorithm for Multisource Energy Harvesting Systems," European Solid-State Circuits Conference(ESSCIRC), 2016.
Joonseok Yang, Minbok Lee, Myeong-Jae Park, Sung-Youb Jung and Jaeha Kim, "A 2.5-V, 160-μJ-Output Piezoelectric Energy Harvester and Power Management IC for Batteryless Wireless Switch (BWS) Applications," Symposium of VLSI Circuits, 2015.

Seuk Son

Alumni

Biography

Seuk Son received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 2013, where he is currently working toward the Ph.D. degree. His research interests include low-power mixedsignal systems and their design methodologies.

2022- Qualcomm, USA
2019-2022 Samsung Electronics, Korea
2019 Ph.D. in E.E.C.S from Seoul National University
2013 B.S. in E.E. from Seoul National University

Email: seuk@mics.snu.ac.kr

Research Interests

Hish speed link IC design, including

High speed transceiver
Low power circuit techniques
Modeling complex mixed system with XMODEL
Cell based automation design flow with XMODEL, PnR tool

Publications

Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," International Solid-State Circuits Conference (ISSCC), 2016.
Seuk Son and Jaeha Kim, "A Noise-Resilient and Ditherless Lock Detection Scheme for Bang-Bang Controlled Calibration Loops," 2015년 한국반도체학술대회 (KCS).
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function," IEEE J. Solid-State Circuits, 2014.
Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyunghoon Kim, E-Hung Chen, Brian Leibowitz, and Jaeha Kim, "A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizing Receiver Front-End and Its Two-Step, Minimum Bit-Error-Rate adaptation Algorithm," IEEE J. Solid-State Circuits, 2013.
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," Custom Integrated Circuits Conference (CICC), 2013.
Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," 2013 VLSI Circuits Symposium.
Jihyun Ryoo, Seuk Son, and Jaeha Kim, "A 25–FO4, 81-mW Radix-64 Crossbar Switch with Partially-Activated Input and Output Lines," International SoC Design Conference 2012.
Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyung Hoon Kim, and Jaeha Kim, "A 2.3-mW, 5-Gb/s Decision-Feedback Equalizing Receiver Front-End with Static-Power-Free Signal Summation and CDR-based Precursor ISI Reduction," IEEE Asian Solid-State Circuits Conference 2012.
Myeong-Jae Park, Hanseok Kim, Seuk Son and Jaeha Kim "A 5-Gbps 1.7pJ/bit Ditherless CDR with Optimal Phase Interval Detection," in IEEE Custom Integrated Circuits Conference, 2012.

Jiho Lee

Alumni

Biography

Jiho Lee received the B.S. degree in electrical and computer engineering from Seoul National University in 2013. He is currently pursuing towards the Ph.D. degree since 2013 in Seoul National University. His research interest includes design automation of analog circuits.

2019- Samsung Electronics, Korea
2019 Ph.D. in E.E.C.S from Seoul National University
2013 B.S. in E.E. from Seoul National University

Email: jhlee@mics.snu.ac.kr

Research Interests

Design automation of analog and mixed signal (AMS) systems, including

Functional verification and equivalence checking of analog-mixed signal models
Simulation-based optimization algorithms for analog circuits
Fault analysis/diagnosis of analog and mixed-signal circuits

My Research Projects

Finished:

Variability-Aware, Discrete Optimization for Analog Circuits
Fault Coverage Analysis of Analog/Mixed-Signal Tests Based on Statistical Dissimilarity
Timing Budget Analysis of DRAM Peripheral Circuits based on Behavioral Model under Power Supply Noise
Circuit-Level Modeling of DRAM Circuits for Full-Chip Timing and Power-Up Verification in SystemVerilog

On-going:

Analog coverage analysis in simulation-driven verification of RF systems

Publications

Yinjae Lee, Jiho Lee, et al. "Analog/Mixed-Signal Verification of DRAM Peripherals with Automatically-Generated System Verilog Models," DAC IP/DT track, 2018.
Jiho Lee and Jaeha Kim, "Efficient Global Optimization of Analog Circuits using Predictive Response Surface Models on Discretized Design Space," IEEE Design & Test, 2016.
Jiho Lee and Jaeha Kim, "Defining a Functional Coverage Metric for Analog Models," Frontiers in Analog CAD (FAC) , 2015.
Jiho Lee and Jaeha Kim, "Investigations on the Optimal Support Vector Machine Classifiers for Predicting Design Feasibility in Analog Circuit Optimization", Journal of Semiconductor Technology and Science (JSTS), 2015.
Jiho Lee and Jaeha Kim, "Predictive Global Optimization Method for Analog Circuit with Response Surface Methodology on Discrete Design Space," Frontiers in Analog CAD (FAC), 2014.
Seobin Jung, Jiho Lee and Jaeha Kim, "Yield-Aware Pareto Front Extraction for Discrete, Hierarchical Optimization of Analog Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2014.
Seobin Jung, Jiho Lee and Jaeha Kim, "Variability-Aware, Discrete Optimization for Analog Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2014.
Jaeha Kim, Jiho Lee, Do-Gyoon Song, Taehwan Kim, Kyung-Hoon Kim, Seobin Jung, Sangho Youn, "Discretization and Discrimination Methods for Design, Verification, and Testing of Analog/Mixed-Signal Circuits," Custom Integrated Circuits Conference (CICC), 2013.

Joonseok Yang

Alumni

Biography

2024- Apple, USA
2024 Ph.D. in Stanford University
2016 M.S. in E.C.E. from Seoul National University
Thesis: Design of an Efficient CapacitorFree Piezoelectric Energy Harvesting PMIC
2014 B.S. in E.C.E. from Seoul National University

Email: brahms@stanford.edu

Research Interests

Mixed Signal Power Management Integrated Circuits (PMIC)

Energy Harvesting System (EHS)

Publications

Wootaek Lim, Joonseok Yang, Myeong-Jae Park and Jaeha Kim, "A 5V, 33-kHz, 0.7-uW Pulse Generation Circuit for Ultra-Low-Power Boost Charging Energy Harvesters," Asian Solid-State Circuits Conference(A-SSCC), 2013.
Joonseok Yang and Jaeha Kim, “Maximum energy transfer condition for piezoelectric energy harvesters with single pulsed vibration inputs,” IET Electronics Letters, Apr. 2014.
Joonseok Yang, Minbok Lee, Myeong-Jae Park, Sung-Youb Jung and Jaeha Kim, "A 2.5-V, 160-μJ-Output Piezoelectric Energy Harvester and Power Management IC for Batteryless Wireless Switch (BWS) Applications," 2015 VLSI Circuits Symposium.
Geon-Tae Hwang, Joonseok Yang et al., “A Reconfigurable Rectified Flexible Energy Harvester via Solid-State Single Crystal Grown PMN–PZT”, Advanced Energy Materials, Mar. 2015.

Juyun Lee

Alumni

Biography

Juyun Lee is currently pursuing the M.S. degree in electrical and computer engineering at Seoul National University. His research interest includes modeling and verification of analog/mixed-signal circuits and systems.

2023- Synopsys, USA
2020-2023 Samsung Electronics, Korea
2016-2019 Coreriver, Korea
2016 M.S. in E.C.E. from Seoul National University
Thesis: A Modeling Methodology for Verification of High-Voltage Wordline Generator in NAND Flash Memory
2013 B.S in E.C.E. from UIUC (University of Illinois at Urbana-Champaign)

Email: jylee@mics.snu.ac.kr

Research Interests

Computer-Aided Design of Analog/Mixed-Signal Circuits and Systems

Modeling high-voltage generating circuits in NAND Flash memory
Modeling temperature compensated self-refresh (TCSR) circuits in DRAM
Performance yield prediction of AMS systems considering process variations

Publications

Juyun Lee, Jeong Yeol Kwon and Jaeha Kim, "Modeling and Simulation of Nonlinear Transient Responses of High-Voltage Wordline Generators in NAND Flash Memories," ISOCC, 2015.
Yoontaek Lee, Juyun Lee, and Jaeha Kim, "GaN FET-based Synchronous Buck Converter with 10-bit 4-MHz Digital Pulse Width Modulator," 2015 ECCE-Asia.

Hyunseung Lee

Alumni

Biography

Hyunseung Lee received the B.S. degree in electrical and computer engineering from Seoul National University in 2014. He is currently working toward the M.S. degree. His research interests include AC input LED driver (for lighting) and energy harvesting systems.

2021- Ph.D. candidate in Seoul National University
2017-2020 AnaPass, Korea
2017 M.S. in E.C.E. from Seoul National University
2014 B.S. in E.C.E. from Seoul National University

Email: hs_lee@snu.ac.kr

Research Interests

AC input LED driver control design
Mixed Signal Integrated Circuits

Energy Harvesting System (EHS)

Se-won Kim

Alumni

Biography

2021- SK Hynix, Korea
2021 M.S. in E.E. from Seoul National University
2018 B.S. in C.S.E.E. from Handong Global University

Email: swkim@mics.snu.ac.kr

Jiyeon Lee

Alumni

Biography

2021- Samsung Electronics, Korea
2021 M.S. in E.E. from Seoul National University
2018 B.S. in E.E. from Hanyang University

Email: jiyeon@mics.snu.ac.kr

Nayoung Choi

Alumni

Biography

2011- Samsung Electronics, Korea
2021 M.S. in E.E. from Seoul National University
2011 B.S. in E.E. from Sungkyunkwan University

Email: nychoi@mics.snu.ac.kr

Chan Young Park

Alumni

Biography

2024- Samsung Electronics, Korea
2021-2024 Telechips, Korea
2021 M.S. in E.E. from Seoul National University
2019 B.S. in E.E. from Sungkyunkwan University

Email: chanyoung@mics.snu.ac.kr

Seoyeong Jo

Alumni

Biography

2022- Shinhan Bank, Korea
2022 M.S. in E.C.E. from Seoul National University
2020 B.S. in E.E. from Seoul National University

Email: seoyeong@mics.snu.ac.kr

Seung Heon Baek

Alumni

Biography

Seung Heon Baek received the B.S degree in electrical engineering from Seoul National University, Seoul, Korea, in 2014. He is currently pursuing the Ph.D. degree in electrical engineering at Seoul National University. His current research interests include design and manage scalable and reconfigurable massive system like crossbar switches, mixed-signal field programmable gate arrays (FPGA) and neuromorphic processing units.

2022- SK Hynix, Korea
2022 Ph.D. in E.C.E. from Seoul National University
2014 B.S. in E.C.E. from Seoul National University

Email: shbaek@mics.snu.ac.kr

Research Interests

Crossbar swithces
Mixed-signal field programmable gate arrays (FPGA)
Neuromorphic processing units

Publications

백승헌, 김재하, "오픈 소스 FPGA 검증 툴 기반 Embedded FPGA의 설계 및 프로그래밍," 한국반도체학술대회, 2016.
Seungheon Baek Sung-Youb Jung, and Jaeha Kim, "Design of Low-Power and Low-Latency 256-Radix Crossbar Switch Using Hyper-X Network Topology," Journal of Semiconductor and Technology Science, 2014.
백승헌, 김재하, "HyperX 구조를 이용한 저전력 256-Radix Crossbar Switch의 설계," 한국반도체학술대회, 2014.