##master-page:HomepageTemplate #format wiki #language en #acl Default All:read <> = About Yunju Choi = == Biography == ## Describe yourself here. ||<
> Yunju Choi received the B.S., M.S., and Ph.D. degrees in electrical engineering from Seoul National University (SNU) in 2011, 2013, 2017, respectively. <
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>'''Contact Information'''<
>''- Email: <>''<
>'' || {{http://mics.snu.ac.kr/wiki/People?action=AttachFile&do=get&target=YUNJU_CHOI.png|YunjuChoi|width="150"}}|| ## You can even more obfuscate your email address by adding more uppercase letters followed by a leading and trailing blank. == Publications == * Yunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, and Jaeha Kim, "A Field-Programmable Mixed-Signal IC with Time-Domain Configurable Analog Blocks," Symposium on VLSI Circuits, 2016 * Minbok Lee, Yunju Choi, Jaeha Kim, "A 500-MHz, 0.76-W/mm2 Power Density and 76.2% Power Efficiency, Fully-Integrated Digital Buck Converter in 65nm CMOS", IEEE Trans. Industry Applications, 2016 * Minbok Lee, Yunju Choi and Jaeha Kim, "A 0.76W/mm2 On-chip Fully-Integrated Buck Converter with Negatively-Coupled, Stacked-LC Filter in 65nm CMOS," Energy Conversion Congress & Expo (ECCE), 2014 * Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," IEEE Symp. on VLSI Circuits, June 2013. * Yunju Choi and Jaeha Kim, "Robust Random Chip ID Generation with Wide-Aperture Clocked Comparators and Maximum Likelihood Detection," IEEE International Symposium on Circuits and Systems, May 2013. * Seobin Jung, Yunju Choi, Jaeha Kim, "Variability-Aware, Discrete Optimization for Analog Circuits," ACM/IEEE Design Automation Conference (DAC), June 2012. * Jaeha Kim, Sigang Ryu, Byoungjoo Yoo, Hanseok Kim, Yunju Choi, and Deog-Kyoon Jeong, "A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs," IEEE International Symposium on Circuits and Systems, May 2012. {{{#!privacy #acl MICSGroup:read ## The contents below are visible only to MICS group members. = Personal Area = == My Research Projects == * [[Collaborative Timing Recovery for 4-PAM Serial Links]] * modeling work with [[doc/xmodel|XMODEL]] * [[Adaptive-Bandwidth Supply-Regulated Phase-Locked Loop]] * [[\Voltage Controlled Oscillator]] * [[Chip-ID Generator Using Low-Noise Comparator Mismatch]] * [[MLD|Maximum-Likelihood Detection Method for Robust Chip-ID generation Using Comparator Mismatch]] ## List your research projects and add links to the project page. If your project page doesn't exist, it's a good idea to add one. == My Research Goals == ## Add links to your yearly accomplishments and objectives pages ## Use "ReflectionsTemplate" * [[/2010 Reflections]] * [[/2012]] == My Research Blogs == <> <> ## Click on the date to create or edit the blogs ||<^><>||<^><>||<^><>|| == My Favorite Links == ## List your favorite links here as desired. }}} ---- CategoryHomepage