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= About Sigang Ryu =

== Biography ==

## Describe yourself here.
||<<BR>> Sigang Ryu received the B.S. degree in electrical engineering from Korea University, Seoul, South Korea, in 2011, and the M.S. and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, in 2014 and 2019, respectively. From the fall of 2021, he has been working as post-doctoral fellow at Georgia Institute of Technology. From 2017 to 2018, he worked as a researcher with the Institute of New Media and Communications (INMC), Seoul National University. From 2019 to 2021, he was a post-doctoral researcher with the Inter-University Semiconductor Research Center (ISRC). His research interests include high-speed timing circuits (D/PLL and CDR), equalizers, ADC, and their design methodologies. For now, his interests also include power-efficient DSP implementation based on various learning algorithms. <<BR>><<BR>>'''Contact Information'''<<BR>>''- Email: sgryu@mics.snu.ac.kr''<<BR>>''||  {{http://mics.snu.ac.kr/wiki/People?action=AttachFile&do=get&target=SIGANG_RYU.png|SigangRyu|height="170"}}||

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== Research Interests ==
## Describe your research interests here.
 * Digital PLL/DLL, CDR for high-speed link system
 * Serdes for high-speed serial links
 * Analog-to-digital converters
 * Automation methodology for implementation of mixed-signal system

== Publications ==
 * Sigang Ryu, Seuk Son and Jaeha Kim, "A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC," IEEE Transactions on Circuits and Systems I (TCAS-I), 2021.
 * Seuk Son, Sigang Ryu, Hwanseok Yeo, and Jaeha Kim, "A 2x Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery," IEEE Journal of Solid-State Circuits (JSSC), 2019
 * Sigang Ryu, Seuk Son and Jaeha Kim, "An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery," IEEE Transactions on Circuits and Systems I (TCAS-I), 2019.
 * Seuk Son, Hwanseok Yeo, Sigang Ryu, and Jaeha Kim, "A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery," IEEE Asian Solid-State Circuits Conference (ASSCC), 2018.
 * Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," IEEE International Solid-State Circuits Conference (ISSCC), 2016.
 * Jaeha Kim, Hwanseok Yeo, Sigang Ryu, “Synthesizing Method of Signal Having Variable Frequency and Synthesizer of Signal Having Variable Frequency,” US Patent App. 2014/604533, filed Jan. 2015.
 * Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, and Jaeha Kim "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function" IEEE Journal of Solid-State Circuits (JSSC), Aug. 2014.
 * Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013.
 * Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," IEEE Symposium of VLSI Circuits (SoVC), 2013.
 * Jaeha Kim, Sigang Ryu, Byoungjoo Yoo, Hanseok Kim, Yunju Choi, and Deog-Kyoon Jeong, "A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs," IEEE International Symposium on Circuits and Systems (ISCAS), May 2012.

== My Research Projects ==
 * Collaborative timing recovery for 4-PAM serial links
 * Model-first design flow (cell-based design flow)
 * Digital PLL implementing peaking-less transfer function
 * Digital PLL with sub-ps jitter using high-resolution pipelined ADC

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= Personal Area =

== My Research Goals ==
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 * [[/Goal]]
 * [[attachment:mics_template_2012_1.ppt]]
 * [[/2013 Planning and Reflections]]

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