##master-page:HomepageTemplate #format wiki #language en #acl Default All:read <> = About Seuk Son = == Biography == ||<
> Seuk Son received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 2013, where he is currently working toward the Ph.D. degree. His research interests include low-power mixedsignal systems and their design methodologies.<
><
>'''Contact Information'''<
>''- Email: <>''<
>'' || {{http://mics.snu.ac.kr/wiki/People?action=AttachFile&do=get&target=SEUK_SON.jpg|syjung|width="160"}} || ## You can even more obfuscate your email address by adding more uppercase letters followed by a leading and trailing blank. == Research Interests == Hish speed link IC design, including * High speed transceiver, * Low power circuit techniques, * Modeling complex mixed system with xmodel * Cell based automation design flow with xmodel, PnR tool == Publications == * Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications," International Solid-State Circuits Conference (ISSCC), 2016 * Seuk Son and Jaeha Kim, "A Noise-Resilient and Ditherless Lock Detection Scheme for Bang-Bang Controlled Calibration Loops," 2015년 한국반도체학술대회 (KCS) * Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function," IEEE J. Solid-State Circuits, 2014 * Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyunghoon Kim, E-Hung Chen, Brian Leibowitz, and Jaeha Kim, "A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizing Receiver Front-End and Its Two-Step, Minimum Bit-Error-Rate adaptation Algorithm," IEEE J. Solid-State Circuits, 2013 * Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son and Jaeha Kim, "A 9.2-GHz Digital Phase Locked Loop with Peaking-Free Transfer Function," Custom Integrated Circuits Conference (CICC), 2013 * Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," 2013 VLSI Circuits Symposium * Jihyun Ryoo, Seuk Son, and Jaeha Kim, "A 25–FO4, 81-mW Radix-64 Crossbar Switch with Partially-Activated Input and Output Lines," International SoC Design Conference 2012 * Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyung Hoon Kim, and Jaeha Kim, "A 2.3-mW, 5-Gb/s Decision-Feedback Equalizing Receiver Front-End with Static-Power-Free Signal Summation and CDR-based Precursor ISI Reduction," IEEE Asian Solid-State Circuits Conference 2012 * Myeong-Jae Park, Hanseok Kim, Seuk Son and Jaeha Kim "A 5-Gbps 1.7pJ/bit Ditherless CDR with Optimal Phase Interval Detection," in IEEE Custom Integrated Circuits Conference, 2012. {{{#!privacy #acl MICSGroup:read ## The contents below are visible only to MICS group members. = Personal Area = == My Research Projects == ## List your research projects and add links to the project page. If your project page doesn't exist, it's a good idea to add one. * Samsung task * SK Hynix task }}} ---- CategoryHomepage