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= About Kyunghoon Kim ( William K. Kim) =
== Biography ==


## Describe yourself here.
||<<BR>> Kyung Hoon Kim is currently working toward the Ph.D. degree in electrical engineering at Seoul National University. He received B.S. and M.S. degrees in electrical engineering from Korea University in 2000 and 2002 respectively. He joined the Hynix semiconductor inc. from 2002 to 2011. During in 10 years at Hynix, had succeed the four mass produce, and had join to develop the first DDR3 & GDDR5 group –JEDEC, and closed community. The Hynix' GDDR5 showed the best speed performance – 5Gbps - in a world. He has published 6 papers and holds more than 60 US patents. The current research area is analog & mixed circuit design for test, and high speed interface for customized memory products. <<BR>><<BR>>'''Contact Information'''<<BR>>''- Email: khkim AT mics.snu.ac.kr''<<BR>>'' || {{http://mics.snu.ac.kr/wiki/People?action=AttachFile&do=get&target=KYUNGHOON_KIM.png|khkim|width="160"}} ||


 

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== Research Interests ==
 * Analog & Mixed Signal Design Verification 
  * Mixed signal test methodology - ATPG for mixed signal circuit 
  * Design for Test and Built In Self Test Circuit for the high speed serial link  
  * Mass production testing methodology - High speed wafer test interface
 * Circuit related to DRAM 
  * Next generation interface for the new memory architecture (TSV) 
  * The timing circuit such as all digital delay locked loop, real time domain crossing circuit
  * The negative resistance termination for cancelling channel impedance mismatch in the multi-drop channel 


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= Personal Area =


== My Research Projects ==
## List your research projects and add links to the project page. If your project page doesn't exist, it's a good idea to add one.
|| - Multi-drop channel compensation method ||
|| - Analog & Mixed System Test Methodology ||
|| - Digilog circuits : The analog circuit follows digital design method ||

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= My Research Goals =

== Publications ==
 1.  !KyungHoon Kim, Jaeha Kim, "Investigations on the Use of Negative-Resistance Terminations for Multi-Drop Bus Channels," in Proc. IEEE International Midwest Symposium on Circuits and Systems,  Aug. 2011.
 2.  Kyunghoon Kim, Jaeha Kim, "Fault Coverage Analysis on Analog/Mixed-Signal Circuits Based on Statistical Dissimilarity," poster session in IEEE Int’ Test Conf., Nov. 2012.
 3.  Kyunghoon Kim, Seuk Son, Sigang Ryu, Hwanseok Yeo, Yunju Choi, and Jaeha Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," in IEEE Symp. on VLSI Circuits, Jun. 2013. 
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== My Research Blogs & Projects ==
## Use "ReflectionsTemplate"
 * [[/2011 Reflections]]
 * [[/2013 Planning and Reflections]]
 * [[/Engineering_note]]
 * [[https://app.asana.com/0/480250438729/480250438729|{{https://app.asana.com/-/static/apps/asana/view/logo_glow.png}}|target="_blank"]]
 * [[http://mics.snu.ac.kr/wiki/Projects%20Home/Sphinx|Sphinx]]
 * [[http://mics.snu.ac.kr/wiki/Projects%20Home/Aquarius|Aquarius]]
<<NewBlog(BlogTemplate, Create/Edit Today's Blog, @ME)>>
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== My Calendar ==
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== My Favorite Links ==
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