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= About jhlee =

== Biography ==
||<<BR>> Jiho Lee received the B.S. degree in electrical and computer engineering from Seoul National University in 2013. He is currently pursuing towards the Ph.D. degree since 2013 in Seoul National University. His research interest includes design automation of analog circuits.<<BR>><<BR>>'''Contact Information'''<<BR>>''- Email: jhlee@mics.snu.ac.kr''<<BR>>'' || {{http://mics.snu.ac.kr/wiki/People?action=AttachFile&do=get&target=JIHO_LEE.jpg|JihoLee|width="160"}} ||


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== Research Interests ==
Design automation of analog and mixed signal (AMS) systems, including
 * Functional verification of analog-mixed signal models
 * Simulation-based optimization algorithms for analog circuits
 * Fault analysis/diagnosis of analog and mixed-signal circuits

== My Research Projects ==
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Finished:
 * Variability-Aware, Discrete Optimization for Analog Circuits
 * Fault Coverage Analysis of Analog/Mixed-Signal Tests Based on Statistical Dissimilarity
 * Timing Budget Analysis of DRAM Peripheral Circuits based on Behavioral Model under Power Supply Noise
 * Circuit-Level Modeling of DRAM Circuits for Full-Chip Timing and Power-Up Verification in System Verilog

On-going:
 * Analog coverage analysis in simulation-driven verification of RF systems

== Publications ==
 * Yinjae Lee, '''Jiho Lee''', et al. "Analog/Mixed-Signal Verification of DRAM Peripherals with Automatically-Generated System Verilog Models," DAC IP/DT track, 2018
 * '''Jiho Lee''' and Jaeha Kim, "Efficient Global Optimization of Analog Circuits using Predictive Response Surface Models on Discretized Design Space," IEEE Design & Test, 2016
 * '''Jiho Lee''' and Jaeha Kim, "Defining a Functional Coverage Metric for Analog Models," Frontiers in Analog CAD (FAC) , 2015
 * '''Jiho Lee''' and Jaeha Kim, "Investigations on the Optimal Support Vector Machine Classifiers for Predicting Design Feasibility in Analog Circuit Optimization", Journal of Semiconductor Technology and Science (JSTS), 2015
 * '''Jiho Lee''' and Jaeha Kim, "Predictive Global Optimization Method for Analog Circuit with Response Surface Methodology on Discrete Design Space," Frontiers in Analog CAD (FAC), 2014
 * Seobin Jung, '''Jiho Lee''' and Jaeha Kim, "Yield-Aware Pareto Front Extraction for Discrete, Hierarchical Optimization of Analog Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2014
 * Seobin Jung, '''Jiho Lee''' and Jaeha Kim, "Variability-Aware, Discrete Optimization for Analog Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2014
 * Jaeha Kim, '''Jiho Lee''', Do-Gyoon Song, Taehwan Kim, Kyung-Hoon Kim, Seobin Jung, Sangho Youn, "Discretization and Discrimination Methods for Design, Verification, and Testing of Analog/Mixed-Signal Circuits," Custom Integrated Circuits Conference (CICC), 2013

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