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= About Eunseo Kim =
== Biography ==

||<<BR>> Eunseo Kim is currently working toward the M.S. degree in Electrical Engineering at Seoul National University (SNU) and his current research interests include low-power mixed-signal systems and their design methodologies. He received the B.S. degree in Physics with an additional major in Electrical Engineering from SNU in 2016.<<BR>><<BR>>'''Contact Information'''<<BR>>''- Email: <<MailTo(eunseo AT SPAMFREE mics DOT snu DOT ac DOT kr)>>''<<BR>>'' || {{attachment:eunseo_profile.png|syjung|width="160"}} ||

== Research Interests ==
 * Cell-Based Design Flow
 * High-Performance PLL Design using Digital Techniques
 * Mixed-Signal High-Speed Link Architecture
  
== Publications ==
 * Eunseo Kim and Jaeha Kim, "A Constant Relative-Gain DCO with Pseudo-Exponential DAC and FVC Feedback for a Constant Loop-Bandwidth PLL", International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2015

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= Personal Area =

== My Research Projects ==
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 * Cell-Based PLL
 * Voltage and Temperature Drift Self-Compensation Clock Tree

== My Research Goals ==
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== My Research Blogs ==

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== My Calendar ==
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== My Favorite Links ==
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