div8_mphase
 vss 36
 vdd 20
 clk_out[7] 2
 clk_out[6] 2
 clk_out[5] 2
 clk_out[4] 2
 clk_out[3] 2
 clk_out[2] 2
 clk_out[1] 2
 clk_out[0] 2
 clk_inp 1
 clk_inn 1
 reset_n 1
gro_tdc
 vss 36
 vdd 20
 up[5] 2
 up[4] 2
 up[3] 2
 up[2] 2
 up[1] 2
 up[0] 2
 reset_n 1
 prop_up 2
 prop_dn 2
 f_range[1] 1
 f_range[0] 1
 dn[5] 2
 dn[4] 2
 dn[3] 2
 dn[2] 2
 dn[1] 2
 dn[0] 2
 clk_ref 1
 clk_fb 1
lcdco
 vss 36
 vdd 20
 reset_n 1
 prop_up 1
 prop_dn 1
 in_dsm[2] 1
 in_dsm[1] 1
 in_dsm[0] 1
 in[9] 1
 in[8] 1
 in[7] 1
 in[6] 1
 in[5] 1
 in[4] 1
 in[3] 1
 in[2] 1
 in[1] 1
 in[0] 1
 dco_pgain[2] 1
 dco_pgain[1] 1
 dco_pgain[0] 1
 clk_lf 1
 clk_outp 2
 clk_outn 2
bbpd
 vss 36
 vdd 20
 up 2
 dn 2
 clk_ref 1
 clk_fb 1
divider
 vss 36
 vdd 20
 clk_outp 2
 clk_outn 2
 clk_inp 1
 clk_inn 1
 reset_n 1
 div_sel[2] 1
 div_sel[1] 1
 div_sel[0] 1
bbpfd
 vss 36
 vdd 20
 up 2
 prop_up 2
 prop_dn 2
 dn 2
 clk_ref 1
 clk_fb 1
ring_dco
 vss 36
 vdd 20
 reset_n 1
 prop_up 1
 prop_dn 1
 in_dsm[2] 1
 in_dsm[1] 1
 in_dsm[0] 1
 in[9] 1
 in[8] 1
 in[7] 1
 in[6] 1
 in[5] 1
 in[4] 1
 in[3] 1
 in[2] 1
 in[1] 1
 in[0] 1
 dco_pgain[2] 1
 dco_pgain[1] 1
 dco_pgain[0] 1
 clk_out[7] 2
 clk_out[6] 2
 clk_out[5] 2
 clk_out[4] 2
 clk_out[3] 2
 clk_out[2] 2
 clk_out[1] 2
 clk_out[0] 2
 clk_lf 1
prescaler
 vss 36
 vdd 20
 reset_n 1
 div_sel[1] 1
 div_sel[0] 1
 clk_outp 2
 clk_outn 2
 clk_inp 1
 clk_inn 1
ph_rotator
 vss 36
 vdd 20
 reset_n 1
 phsel[6] 1
 phsel[5] 1
 phsel[4] 1
 phsel[3] 1
 phsel[2] 1
 phsel[1] 1
 phsel[0] 1
 f_range[1] 1
 f_range[0] 1
 clk_outb 2
 clk_out 2
 clk_in[7] 1
 clk_in[6] 1
 clk_in[5] 1
 clk_in[4] 1
 clk_in[3] 1
 clk_in[2] 1
 clk_in[1] 1
 clk_in[0] 1
